Ultra Thin Body Silicon-On-Insulator (UTB SOI) MOSFET with Metal Gate Work-function Engineering for sub-70 nm Technology Node

2002 ◽  
Author(s):  
Daewon Ha ◽  
Pushkar Ranade ◽  
Yang-Kyu Choi ◽  
Jeong-Soo Lee ◽  
Tsu-Jae King ◽  
...  

Ultra Thin Body Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistors (UTB-SOI-MOSFETs) provide better immunity to Short Channel Effects (SCEs). But the behaviour changes at miniaturization and still the many unexplored effects need to be analysied. Here in this paper, Drain Induced Barrier Lowering (DIBL) and sub-threshold Slope (SS) variation of a n-channel UTB-SOI-MOSFET have been analyzed by changing the device structural aspects like gate length (LG), BOX thickness (tBOX) and Silicon film thickness (tSi). Also, the effect of intrinsic parameters as metal gate work function and channel material variation on DIBL and sub-threshold Slope (SS) variation has been analyzed


2003 ◽  
Vol 42 (Part 1, No. 4B) ◽  
pp. 1979-1982 ◽  
Author(s):  
Daewon Ha ◽  
Pushkar Ranade ◽  
Yang-Kyu Choi ◽  
Jeong-Soo Lee ◽  
Tsu-Jae King ◽  
...  

2011 ◽  
Vol 2 (1) ◽  
pp. 11-24 ◽  
Author(s):  
Deepesh Ranka ◽  
Ashwani K. Rana ◽  
Rakesh Kumar Yadav ◽  
Kamalesh Yadav ◽  
Devendra Giri

2010 ◽  
Vol 87 (9) ◽  
pp. 1805-1807 ◽  
Author(s):  
Zilan Li ◽  
Tom Schram ◽  
Thomas Witters ◽  
Joshua Tseng ◽  
Stefan De Gendt ◽  
...  

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.


2005 ◽  
Vol 80 ◽  
pp. 280-283 ◽  
Author(s):  
G. Sjöblom ◽  
L. Pantisano ◽  
T. Schram ◽  
J. Olsson ◽  
V. Afanas’ev ◽  
...  

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