scholarly journals Silicon Die with Integrated Epoxy for Improved Interface Adhesion

Author(s):  
F. R. Gomez ◽  
R. Rodriguez

Breakthroughs and innovations are constantly being developed in electronic packaging industry to address the manufacturing challenges and overcome existing assembly limitations. An augmented design of thin Silicon die is introduced to establish a robust and improved interface adhesion between the die and the die attach material during the die attach process. The wafer preparation flow is also presented. The realization of the augmented die design with integrated epoxy material would ultimately provide a robust connection and would mitigate the die attach related issues such delamination, die cracks and voids.

Author(s):  
Rennier S. Rodriguez ◽  
Frederick Ray I. Gomez

Innovations and breakthroughs are continuously driven in semiconductor manufacturing to overcome existing assembly limitations and recurring difficulties. This paper is focused on the resolution of the delamination issue during die attach assembly process. A new design of semiconductor die is presented to establish a robust adhesion or interface bonding between the silicon die and the epoxy material for die attach. The paper also provides the specialized design of manufacturing flow for the improved die design through advanced wafer fabrication method and wafer cutting technique. The realization of the advanced silicon die design would ultimately mitigate the delamination issue and would contribute for a robust die attach assembly process.


2014 ◽  
Vol 26 (3) ◽  
pp. 147-161 ◽  
Author(s):  
Ervina Efzan Mhd Noor ◽  
Amares Singh

Purpose – The aim of the present study was to gather and review all the important properties of the Sn–Ag–Cu (SAC) solder alloy. The SAC solder alloy has been proposed as the alternative solder to overcome the environmental concern of lead (Pb) solder. Many researchers have studied the SAC solder alloy and found that the properties such as melting temperature, wettability, microstructure and interfacial, together with mechanical properties, are better for the SAC solder than the tin – lead (SnPb) solders. Meanwhile, addition of various elements and nanoparticles seems to produce enhancement on the prior bulk solder alloy as well. These benefits suggest that the SAC solder alloy could be the next alternative solder for the electronic packaging industry. Although many studies have been conducted for this particular solder alloy, a compilation of all these properties regarding the SAC solder alloy is still not available for a review to say. Design/methodology/approach – Soldering is identified as the metallurgical joining method in electronic packaging industry which uses filler metal, or well known as the solder, with a melting point < 425°C (Yoon et al., 2009; Ervina and Marini, 2012). The SAC solder has been developed by many methods and even alloying it with some elements to enhance its properties (Law et al., 2006; Tsao et al., 2010; Wang et al., 2002; Gain et al., 2011). The development toward miniaturization, meanwhile, requires much smaller solder joints and fine-pitch interconnections for microelectronic packaging in electronic devices which demand better solder joint reliability of SAC solder Although many studies have been done based on the SAC solder, a review based on the important characteristics and the fundamental factor involving the SAC solder is still not sufficient. Henceforth, this paper resolves in stating all its important properties based on the SAC solder including its alloying of elements and nanoparticles addition for further understanding. Findings – Various Pb-free solders have been studied and investigated to overcome the health and environmental concern of the SnPb solder. In terms of the melting temperature, the SAC solder seems to possess a high melting temperature of 227°C than the Pb solder SnPb. Here, the melting temperature of this solder falls within the range of the average reflow temperature in the electronic packaging industry and would not really affect the process of connection. A good amendment here is, this melting temperature can actually be reduced by adding some element such as titanium and zinc. The addition of these elements tends to decrease the melting temperature of the SAC solder alloy to about 3°C. Adding nanoparticles, meanwhile, tend to increase the melting temperature slightly; nonetheless, this increment was not seemed to damage other devices due to the very slight increment and no drastic changes in the solidification temperature. Henceforth, this paper reviews all the properties of the Pb-free SAC solder system by how it is developed from overcoming environmental problem to achieving and sustaining as the viable candidate in the electronic packaging industry. The Pb-free SAC solder can be the alternative to all drawbacks that the traditional SnPb solder possesses and also an upcoming new invention for the future needs. Although many studies have been done in this particular solder, not much information is gathered in a review to give better understanding for SAC solder alloy. In that, this paper reviews and gathers the importance of this SAC solder in the electronic packaging industry and provides information for better knowledge. Originality/value – This paper resolves in stating of all its important properties based on the SAC solder including its alloying of elements and nanoparticles addition for further understanding.


Author(s):  
Jerome J. Dinglasan ◽  
Frederick Ray I. Gomez

As the modern world evolves through innovation and technology, manufacturing companies of semiconductor drive their people to dedicate themselves on continuous improvement and technical advancement. Products they produce becomes smaller and thinner, but applications are limitless and innovative. In manufacturing of quad flat no lead packages, challenges were encountered during the die attach process especially in small die size. Die attach material overflow on pad is one of these, and certain parameters and techniques are explored to have a quality and robust process. Defining appropriate epoxy pattern with respect to the die size is a big factor to make sure no epoxy material will flow outside the die pad perimeter that may cause unit rejection. This paper will discuss the related issues of the said package by performing experiments and applying certain techniques to address the problem.


2013 ◽  
Vol 795 ◽  
pp. 522-525 ◽  
Author(s):  
S.I. Najib ◽  
Mohd Arif Anuar Mohd Salleh ◽  
Saud Norainiza

Nowadays, excessive growth intermetallic formation becomes the major issue in electronic packaging industry. The investigation on the effect of aging temperature to the intermetallic compound (IMCs) growth formation for Sn-0.7Cu/1.0-Si3N4 was studied. Isothermal aging process was carried out for 24 hours, with 5 difference aging temperature from 50°C up to 150°C. It is found that the Cu-Sn IMCs which appear after reflowed process, has grew rapidly when aging temperature was increased up to 125°C and started to reduced after 150°C aging temperature.


Author(s):  
Rennier S. Rodriguez ◽  
Frederick Ray I. Gomez ◽  
Bryan Christian S. Bacquian

Process improvement through modification in the design of indirect material is one potential direction to improve the productivity during assembly manufacturing. In this paper, an augmented design of anvil block is presented to reduce the crumpled strips, leadframe bending and dents, uneven bonding of die, localized insufficient epoxy, and misaligned die encountered during the conversion and setup stage. The implementation of the augmented design improves the current assembly practice through eliminating the replacement of anvil block that is the cause of misalignment on the indexer handler of the die attach machine. Through this design, the selection of appropriate vacuum hole setup can be through the sliding insert only without pulling out the anvil block from the machine.


Author(s):  
Don Schatzel

Miniaturization of electronic packages will play a key role in future space avionics systems. Smaller avionics packages will reduce payloads while providing greater functionality for information processing and mission instrumentation. Current surface mount technology discrete passive devices not only take up significant space but also add weight. To that end, the use of embedded passive devices, such as capacitors, inductors and resistors will be instrumental in allowing electronics to be made smaller and lighter. Embedded passive devices fabricated on silicon or like substrates using thin film technology, promise great savings in circuit volume, as well as potentially improving electrical performance by decreasing parasitic losses. These devices exhibit a low physical profile and allow the circuit footprint to be reduced by stacking passive elements within a substrate. Thin film technologies used to deposit embedded passive devices are improving and costs associated with the process are decreasing. There are still many challenges with regard to this approach that must be overcome. In order to become a viable approach these devices need to work in conjunction with other active devices such as bumped die (flip chip) that share the same substrate area. This dictates that the embedded passive devices are resistant to the subsequent assembly processes associated with die attach (temperature, pressure). Bare die will need to be mounted directly on top of one or more layers of embedded passive devices. Currently there is not an abundant amount of information available on the reliability of these devices when subjected to the high temperatures of die attach or environmental thermal cycling for space environments. Device performance must be consistent over time and temperature with minimal parasitic loss. Pretested and assembled silicon substrates with layers of embedded capacitors made with two different dielectric materials, Ta2O5 (Tantalum Oxide) and benzocyclobutene (BCB), were subjected to the die attach process and tested for performance in an ambient environment. These assemblies were subjected to environmental thermal cycling from −55°C to 100°C. Preliminary results indicate embedded passive capacitors and resistors can fulfill the performance and reliability requirements of space flight on future missions. Testing results are encouraging for continued development of integrating embedded passive devices to replace conventional electronic packaging methods.


Author(s):  
Meiyu Wang ◽  
Yun-Hui Mei ◽  
Jingyou Jin ◽  
Shi Chen ◽  
Xin Li ◽  
...  

2019 ◽  
Vol 2019 (1) ◽  
pp. 000545-000549
Author(s):  
Be-nazir Khan

Abstract A detailed computational fluid dynamic based thermal model and simulation of exposed pad SOIC package on PCB is developed with Nano and gold-based material to characterize the thermal behavior or cooling capability of the package. Achieving lower thermal resistance of electronic packaging is one of the important points of interest in electronic application. In this paper, exposed small outline IC package on PCB is compared with different composition of Au-Sn die attach materials and Nano-foil preform material to understand the thermal behavior of the package which will provide cooling through low thermal resistance between junction-to-case. Thermal reliability of electronic packaging depends on the package design and selection of materials. Package material design plays an important role in thermal management of the product. Nano-based package material can be a good choice to improve the thermal performance of system on package. Developed a 3 D model of exposed small outline IC (E-SOIC) package on a printed circuit board (PCB). Au-Sn solder paste is used as die attach material and Nano-Foil preform is used to develop the system on package (SOP) model of exposed pad SOIC package on PWB. Different types of composition of Au-Sn solder paste, such as 78Au22Sn and 80Au20Sn are considered for die attach purpose. The reason for choosing the AuSn solder paste is good reliability and performance. Au-Sn has higher thermal conductivity than other solder materials, such as Pb-free solder paste, 96.5Sn3.5Ag and leaded solder paste, 37Pb63Sn. Two types of thermal model developed to compare the package material and design of the different die attach materials and Nano-Foil preforms. In this paper simulation and data analysis will show how the optimum thermal management depends on the material selection and design of the system on package (SOP). Surface mount type SOIC package with exposed pad design is selected to enhance the thermal purpose. Gold-tin and Nano-Foil preform will be used as alternative of lead-free package materials.


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