Development of Reliable Electronic Packaging Solutions for Spacecraft Avionics Miniaturization Using Embedded Passive Devices

2003 ◽  
Author(s):  
Don Schatzel
Keyword(s):  
Thin Film ◽  
Thermal Cycling ◽  
Electronic Packaging ◽  
Flip Chip ◽  
Dielectric Materials ◽  
Electrical Performance ◽  
Passive Devices ◽  
Die Attach ◽  
Space Environments ◽  
Viable Approach

Miniaturization of electronic packages will play a key role in future space avionics systems. Smaller avionics packages will reduce payloads while providing greater functionality for information processing and mission instrumentation. Current surface mount technology discrete passive devices not only take up significant space but also add weight. To that end, the use of embedded passive devices, such as capacitors, inductors and resistors will be instrumental in allowing electronics to be made smaller and lighter. Embedded passive devices fabricated on silicon or like substrates using thin film technology, promise great savings in circuit volume, as well as potentially improving electrical performance by decreasing parasitic losses. These devices exhibit a low physical profile and allow the circuit footprint to be reduced by stacking passive elements within a substrate. Thin film technologies used to deposit embedded passive devices are improving and costs associated with the process are decreasing. There are still many challenges with regard to this approach that must be overcome. In order to become a viable approach these devices need to work in conjunction with other active devices such as bumped die (flip chip) that share the same substrate area. This dictates that the embedded passive devices are resistant to the subsequent assembly processes associated with die attach (temperature, pressure). Bare die will need to be mounted directly on top of one or more layers of embedded passive devices. Currently there is not an abundant amount of information available on the reliability of these devices when subjected to the high temperatures of die attach or environmental thermal cycling for space environments. Device performance must be consistent over time and temperature with minimal parasitic loss. Pretested and assembled silicon substrates with layers of embedded capacitors made with two different dielectric materials, Ta2O5 (Tantalum Oxide) and benzocyclobutene (BCB), were subjected to the die attach process and tested for performance in an ambient environment. These assemblies were subjected to environmental thermal cycling from −55°C to 100°C. Preliminary results indicate embedded passive capacitors and resistors can fulfill the performance and reliability requirements of space flight on future missions. Testing results are encouraging for continued development of integrating embedded passive devices to replace conventional electronic packaging methods.

Active and Passive Devices Embedded in Laminate-Based Multilayer Board

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001253-001283
Author(s):  
Satoshi Okude ◽  
Kazushisa Itoi ◽  
Masahiro Okamoto ◽  
Nobuki Ueta ◽  
Osamu Nakao
Keyword(s):  
High Temperature ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Wafer Level ◽  
Active Device ◽  
Electrical Connection ◽  
Passive Devices ◽  
High Temperature Storage ◽  
Circuit Resistance ◽  
Temperature Storage

We have developed active and passive devices embedded multilayer board utilizing our laminate-based WLCSP embedding technology. The proposed embedded board is realized by laminating plural circuit formed polyimide films together by adhesive with thin devices being arranged in between those polyimide layers. The electrical connection via has a filled via structure composed of the alloy forming conductive paste which ensures high reliable connection. The embedded active device is WLCSP which has no solder bump on its pads therefore the thickness of the die is reduced to 80 microns. The embedded passive device is a chip resistor or capacitor whose thickness is 150 microns with copper electrodes. The electrical connection between components and board's circuits are made by same conductive paste vias. The thin film based structure and low profile devices yields the 260 microns thickness board which is the thinnest embedded of its kind in the world. To confirm the reliability of the embedded board, we have performed several reliability tests on the WLCSP and resistors embedded TEG board of 4 polyimide/5 copper circuit layers. As environmental tests, we performed a moisture reflow test compliant to JEDEC MSL2 followed by a thermal cycling test (−55 deg.C to 125 deg.C, 1000cycles) and a high temperature storage test (150 deg.C). All tested samples passed the moisture reflow test and showed no significant change of circuit resistance after the thermal cycling/high temperature storage tests. Moreover, mechanical durability of the board was also confirmed by bending the devices embedded portion. The embedded device was never broken and the circuit resistance change was also within acceptable range. The proposed embedded board will open up a new field of device packaging. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-3-12.

Design, Fabrication, Electrical Characterization and Reliability of Nanomaterials Based Embedded Passives

2010 ◽  
Vol 2010 (1) ◽  
pp. 000847-000854 ◽  
Author(s):  
Rabindra N. Das ◽  
John M. Lauffer ◽  
Steven G. Rosser ◽  
Mark D. Poliks ◽  
Voya R. Markovich
Keyword(s):  
Thin Film ◽  
Flip Chip ◽  
Electrical Performance ◽  
Large Area ◽  
Capacitance Density ◽  
High Capacitance ◽  
Embedded Passives ◽  
Internal Core ◽  
Embedded Resistors ◽  
Carbon Based

This paper discusses thin film technology based on barium titanate (BaTiO3)-epoxy polymer nanocomposites. In particular, we highlight recent developments on high capacitance, large area, thin film passives and their integration in System in a Package (SiP). A variety of nanocomposite thin films ranging from 2 microns to 25 microns thick were processed on PWB substrates by liquid coating or printing processes. SEM micrographs showed uniform particle distribution in the coatings. The electrical performance of composites was characterized by dielectric constant (Dk), capacitance and dissipation factor (loss) measurements. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on resistors and capacitors. Two basic capacitor cores were used for this study. One is a layer capacitor. The second capacitor in this case study was discrete capacitor. Resin Coated Copper Capacitive (RC3) nanocomposites were used to fabricate 35 mm substrates with a two by two array of 15mm square isolated epoxy based regions; each having two to six RC3 based embedded capacitance layers. Cores are showing high capacitance density ranging from 15 nF to 30nF depending on Cu area, composition and thickness of the capacitors. In another design, we have used eight layer high density internal core and subsequent fine geometry n (1 to 3) buildup layers to form a n-8-n structure. The eight layer internal core has two resistance layers in the middle and 2 to 6 capacitance layer sequentially applied on the surface. The study also evaluates the resistor materials for embedded passives. Resistors are carbon based pastes and metal based alloys NiCrAlSi. Embedded resistor technology can use either thin film materials, that are applied on the copper foil, or screened carbon based resistor pastes that can achieve any resistor value at any level. For example, combination of 25 ohm per square material and 250 ohm per square material enables resistor ranges from 15 ohms through 30,000 ohms with efficient sizes for the embedded resistors. Similarly, printable resistors can be designed to cover the resistance in the range of 5 ohms to 1 Mohm. The embedded resistors can be laser trimmed to a tolerance of <5% for applications that require tighter tolerance. Reliability of the test vehicles was ascertained by IR-reflow, thermal cycling, PCT (Pressure Cooker Test ) and solder shock. Embedded discrete capacitors were stable after PCT and solder shock. Capacitance change was less than 5% after IR reflow (assembly) preconditioning (3X, 245 °C) and 1400 cycles DTC (Deep Thermal Cycle).

Experimental and Numerical Investigation of the Reliability of Double-Sided Area Array Assemblies

2006 ◽  
Vol 128 (4) ◽  
pp. 441-448 ◽  
Author(s):  
S. Chaparala ◽  
J. M. Pitarresi ◽  
S. Parupalli ◽  
S. Mandepudi ◽  
M. Meilunas
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Mirror Image ◽  
Circuit Board ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Area Array ◽  
Plastic Ball

One of the primary advantages of surface mount technology (SMT) over through-hole technology is that SMT allows the assembly of components on both sides of the printed circuit board (PCB). Currently, area array components such as ball grid array (BGA) and chip-scale package (CSP) assemblies are being used in double-sided configurations for network and memory device applications as they reduce the routing space and improve electrical performance (Shiah, A. C., and Zhou, X., 2002, “A Low Cost Reliability Assessment for Double-Sided Mirror-Imaged Flip Chip BGA Assemblies,” Proceedings of the Seventh Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 7–15, and Xie, D., and Yi, S., 2001, “Reliability Design and Experimental work for Mirror Image CSP Assembly”, Proceedings of the International Symposium on Microelectronics, Baltimore, October, pp. 417–422). These assemblies typically use a “mirror image” configuration wherein the components are placed on either side of the PCB directly over each other; however, other configurations are possible. Double-sided assemblies pose challenges for thermal dissipation, inspection, rework, and thermal cycling reliability. The scope of this paper is the study of the reliability of double-sided assemblies both experimentally and through numerical simulation. The assemblies studied include single-sided, mirror-imaged, 50% offset CSP assemblies, CSPs with capacitors on the backside, single-sided, mirror-imaged plastic ball grid arrays (PBGAs), quad flat pack (QFP)/BGA mixed assemblies. The effect of assembly stiffness on thermal cycling reliability was investigated. To assess the assembly flexural stiffness and its effect on the thermal cycling reliability, a three-point bending measurement was performed. Accelerated thermal cycling cycles to failure were documented for all assemblies and the data were used to calculate the characteristic life. In general, a 2X to 3X decrease in reliability was observed for mirror-image assemblies when compared to single-sided assemblies for both BGAs and CSPs on 62mil test boards. The reliability of mirror-image assemblies when one component was an area array device and the other was a QFP was comparable to the reliability of the single-sided area array assemblies alone, that is, the QFP had almost no influence on the double-sided reliability when used with an area array component. Moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux’s crack propagation method.

Investigation of Variable Frequency Microwave Processing for Electronic Packaging Applications

2003 ◽  
Vol 125 (2) ◽  
pp. 294-301 ◽  
Author(s):  
Patricia F. Mead ◽  
Aravind Ramamoorthy ◽  
Shapna Pal
Keyword(s):  
Electronic Packaging ◽  
Flip Chip ◽  
Failure Modes ◽  
Electronic Devices ◽  
Electrical Performance ◽  
Variable Frequency ◽  
Operating Parameters ◽  
Radiation Stress ◽  
Convection Oven ◽  
Electrical Degradation

This paper summarizes the effects of the variable frequency microwave (VFM) technique for rapid cure of polymeric encapsulants (such as flip-chip underfills) on the performance and reliability of electronic devices. Initial electrical performance of selected commercial IC packages following the application of VFM radiation stress has been recorded, and the performance has been compared to packages that were treated with comparable temperature cycles as applied in a convection oven. Failure analysis was performed on packages that showed electrical degradation to identify likely degradation and failure modes of the packaged ICs. Overall, our results show that VFM technology can safely be applied as an electronic packaging technology. However, proper control of VFM operating parameters is needed to ensure favorable performance of electronic devices.

Co-optimized Reliability and Parasitic inductance in Small Footprint Vertical Silicon Carbide MOSFET

2018 ◽  
Vol 2018 (HiTEC) ◽  
pp. 000087-000092
Author(s):  
M. Montazeri ◽  
S. Seal ◽  
A. Wallace ◽  
A. Mantooth ◽  
D. Huitink
Keyword(s):  
Silicon Carbide ◽  
Thermal Cycling ◽  
Power Electronics ◽  
Flip Chip ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Element Analysis ◽  
Great Opportunity ◽  
Parasitic Inductance ◽  
Fea Simulation

Abstract Increasing power density in power electronics is driving a need for improved packaging methods for co-optimized high frequency performance, thermal dissipation and reliable operation, especially at high temperatures. Silicon Carbide (SiC) devices offer great opportunity as wide bandgap semiconductor devices, which maintain stability over wide temperature ranges, especially when compared to Silicon (Si) based devices. A novel flip-chip packaging technique for SiC power devices was developed at the University of Arkansas. This new package re-orients a bare die from a lateral device to a vertical device by utilizing a copper connector that routes the drain connection to the top side of the die. This study involves an investigation of achieving a co-optimized packaging configuration for thermomechanical reliability and low parasitic inductance. By orienting this SiC switch vertically, the unique 3D drain connector dramatically reduces the ringing at aggressive switching speeds used in power electronics when compared to Commercial Off The Shelf (COTS) devices. However, the design of this drain connector holds importance for high temperature operation, interconnect reliability as well as manufacturability. Effects of the packaging design, including materials, layout and solder pitch size were investigated from a thermal cycling reliability aspect. Electrical performance, such as parasitic inductances of the device, was also investigated using Finite Element Analysis (FEA) simulation. Several drain connector architectures were evaluated for their fatigue life capability of solder interconnects under thermal cycling (according to Darveaux's model) in conjunction with the parasitic inductance using FEA simulation. Based on the simulation results, an optimized architecture was selected and fabricated for prototype demonstration, and the electrical performance under double pulse test compared with state of the art devices demonstrated improvement in switching performance by reducing overshoot of voltage across the grain-source by 36% and 77% reduction of the drain current ringing during the turn-off event while eliminating voltage overshoot during turn-on event for the testing conditions.

Thick Film Technology For Today's Hearing Products

2014 ◽  
Vol 2014 (1) ◽  
pp. 000325-000330
Author(s):  
John Dzarnoski ◽  
Susie Johansson
Keyword(s):  
Thick Film ◽  
Hearing Aids ◽  
Electronic Packaging ◽  
Flip Chip ◽  
Telecommunications Industry ◽  
Passive Devices ◽  
3D Packaging ◽  
History Of ◽  
Vertical Interconnect

There has been continuous worldwide effort to increase the volumetric efficiency of electronic packaging. Much of this effort has been driven by the telecommunications industry that has succeeded in reducing cell phone size while simultaneously increasing functionality. The hearing aid business has always had the need to use extremely small electronic packaging because hearing aids pack electronics into the ear canal. The first commercial product using the transistor in 1952 was a hybrid vacuum tube-transistor hearing instrument. Today's hearing aids, such as Starkey's 3-Series product, have significant computing power and run complex hearing algorithms that have enormous impact on a patient's quality of life. The industry trend is to put more memory, more signal processing capability and more wireless capability into hearing aids to increase functionality and to improve performance. In order to achieve this increase in performance, the hearing business has had to develop and execute 3D packaging well ahead of other industries. This paper will examine the history of ceramic hybrid packaging at Starkey. The challenges and drivers for major technology steps will be addressed. The following technical advancements, transitions, considerations and limitations will be examined: changing ASIC technologies, impact of chip metallization, solder interconnect temperature hierarchy, impact of RoHS legislation, overcoming routing design limits, miniaturization realized by flip chip attach, impact of chip stacking on size, migration to stacked thick film ceramic interconnect layers using vertical interconnect channels, advances in thick film materials to support higher interconnect density, and incorporation of integrated passive devices.

Thermally and Electrically Enhanced Wirebond BGA

2013 ◽  
Vol 2013 (1) ◽  
pp. 000478-000483
Author(s):  
Burton Carpenter ◽  
Boon Yew Low ◽  
Leo M. Higgins ◽  
Sriram Neelakantan ◽  
Robert Wenzel ◽  
...  
Keyword(s):  
Flip Chip ◽  
Hold Time ◽  
Thermal Interface Material ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Package Design ◽  
Die Attach ◽  
Bga Package ◽  
End Use ◽  
Set Up

Next-generation processors continue to demand more thermal and electrical performance from the package. Frequently, devices are designed into Flip Chip (FC) packages where the previous generations were in Wire Bond (WB) because FC typically provides superior thermal dissipation and lower package electrical parasitics than WB packages. However, FC packages usually have higher costs for mid-range IO (500–800). An Enhanced WB BGA package has been designed with improved thermal and electrical performance compared to the industry standard TEPBGA-2 (Thermally Enhanced PBGA type 2). The 500μm barrier of mold compound between the die and heatspreader in the TEPBGA-2 is a major impediment to heat flow out of the package. By contrast, the Enhanced WB package uses post-mold attachment of a heat spreader that is adhesively bonded to the mold cap and thermally coupled to the die using a 40μm TIM (thermal interface material). Improvements to substrate design rules and the die attach process that enabled the Enhanced WB design to shorten bond wires by 40% and improved electrical performance. Package thermal resistance, Theta-Ja, was verified by simulation and measurement to be 3C°/W lower than TEPBGA-2, that dissipates up to 15W in some end-use applications, approximately 2× the performance of TEPBGA-2. DDR set-up and hold time showed 30ps improvement by both simulation and measurement. This paper will present the package design, thermal and electrical simulation and measurement results.

Die Stress Variation During Thermal Cycling Reliability Tests

2007 ◽  
Author(s):  
M. Kaysar Rahim ◽  
Jordan Roberts ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall
Keyword(s):  
Thermal Cycling ◽  
Electronic Packaging ◽  
Room Temperature ◽  
Flip Chip ◽  
Constitutive Relations ◽  
Temperature Cycling ◽  
Material Behavior ◽  
Aging Effects ◽  
Test Chips

Thermal cycling accelerated life testing is an established technique for thermo-mechanical evaluation and qualification of electronic packages. Finite element life predictions for thermal cycling configurations are challenging due to several reasons including the complicated temperature/time dependent constitutive relations and failure criteria needed for solders, encapsulants and their interfaces; aging/evolving material behavior for the packaging materials (e.g. solders); difficulties in modeling plating finishes; the complicated geometries of typical electronic assemblies; etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling are difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, little is known about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In this work, we have used test chips containing piezoresistive stress sensors to characterize the in-situ die surface stress during long-term thermal cycling of electronic packaging assemblies. Using (111) silicon test chips, the complete three-dimensional stress state (all 6 stress components) was measured at each rosette site by monitoring the resistance changes occurring in the sensors. The packaging configuration studied in this work was flip chip on laminate where 5 × 5 mm perimeter bumped die were assembled on FR-406 substrates. Three different thermal cycling temperature profiles were considered. In each case, the die stresses were initially measured at room temperature after packaging. The packaged assemblies were then subjected to thermal cycling and measurements were made either incrementally or continuously during the environmental exposures. In the incremental measurements, the packages were removed from the chamber after various durations of thermal cycling (e.g. 250, 500, 750, 1000 cycles, etc.), and the sensor resistances were measured at room temperature. In the continuous measurements, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously during the thermal cycling exposure. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage.

Dielectrics for Organic Transistors with Low Threshold Voltage

2005 ◽  
Vol 871 ◽  
Author(s):  
Jochen Brill ◽  
Silke Goettling ◽  
Eduardo Margallo Balbás
Keyword(s):  
Thin Film ◽  
Electrical Properties ◽  
Thin Film Transistors ◽  
Dielectric Materials ◽  
Organic Thin Film Transistors ◽  
Electrical Performance ◽  
Organic Transistors ◽  
Organic Thin Film ◽  
High K ◽  
Low Threshold

AbstractOrganic thin film transistors for display applications are investigated. Different dielectric materials – inorganic and organic – have been studied with respect to their electrical performance It was found that anodic oxidation is an excellent process to achieve smooth high-k dielectrics with high breakthrough field strength. With the proposed electrolyte electrical properties were further improved. The alignment of pentacene on different insulators as well as transistors characteristics is presented.

Materials in Electronic Manufacturing: Electronic Packaging

MRS Bulletin ◽  
1992 ◽  
Vol 17 (4) ◽  
pp. 38-41
Author(s):  
Robert C. Pfahl
Keyword(s):  
Integrated Circuit ◽  
Electronic Packaging ◽  
Printed Circuit Boards ◽  
Dielectric Material ◽  
Cost Effective ◽  
Dielectric Materials ◽  
Electrical Performance ◽  
Wave Soldering ◽  
Effective Manner ◽  
Planar Substrates

Electronic packaging involves using an appropriate combination of conductive and dielectric materials to electrically interconnect and mechanically support electronic components in a reliable and cost-effective manner. Since the invention of the integrated circuit in 1959 and mass wave-soldering in 1958, the vast majority of electronic packaging has involved a planar substrate to which semiconductor devices in protective packages are attached by melting eutectic solder. The planar substrates or printed circuit boards (PCBs) were invented in 1940, but their widespread implementation was limited until the invention of mass soldering. PCBs use conventional epoxy-glass dielectric material with mass patterned conductive traces of copper, but alternative materials have been used for either enhanced electrical performance or lower product cost.

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