Double Gate Heterostructure Based Tunnel FET with 51.5 mV/decade Subthreshold Slope

2016 ◽  
Vol 06 (05) ◽  
pp. 53-59
Author(s):  
Gagandeep Kaur ◽  
Gurmohan Singh ◽  
Manjit Kaur
2021 ◽  
Author(s):  
Priyanka Karmakar ◽  
P K Sahu

Abstract A Silicon based Vertical Dual metal Double gate Tunnel FET (Si-VDMDGTFET) has been proposed and simulated in Sentaurus TCAD tool with improved DC and analog/RF characteristics. The vertical In-line tunneling dominates in the proposed device which results in better subthreshold slope (SS). The vertical in-line tunneling tunes the tunneling barrier and eventually controls the ON current. The dual metal gate and the heterogeneous gate stack oxide within the proposed device design gives the mouldability for controlling and improving the DC characteristics such as ON current, OFF current. The analog/RF behaviour of the proposed device has been calculated and compared with conventional lateral Silicon based dual metal double gate Tunnel FET furthermore it is seen that the proposed device outperforms the conventional lateral device.


Sign in / Sign up

Export Citation Format

Share Document