Cerium oxide capping on Y-doped HfO2 films for ferroelectric phase stabilization with endurance improvement

The effects of 1-nm-thick CeOx capping on 7.5-nm-thick Y-doped HfO2 films on the ferroelectric characteristics are investigated. From the ferroelectric characteristics of the samples annealed at different temperatures from 450 to 600oC and annealing durations, the time (τ) required to stabilize the ferroelectric phase at each temperature was shortened by the capping. The identical activation energy (Ea) of 2.65 eV for ferroelectric stabilization without and with capping suggests the same kinetics for phase transformation. However, an increase in the remnant polarization (Pr) was obtained. Only a few Ce atoms diffused into the underlying HfO2 film even after 600oC annealing. Ferroelectric switching tests revealed an improvement in endurance from 107 to 1010 by the capping, presumably owing to the suppression of conductive filament formation. Therefore, CeOx capping is effective in promoting the ferroelectric phase in HfO2 with high switching endurance.

Control of global variables for identical and non-identical Josephson junctions arrays

In the paper a way to solve an LQ-problem for a Josephson junction array with a common LRC-load is proposed. The cases of identical and non-identical Josephson junctions are considered. The solution ensures phase stabilization of Josephson current in every junction. The results are obtained using computer simulation in Jupyter Notebook and MATLAB.

Low-power 25Gb/s 16:1 Multiplexer for 400Gb/s Ethernet PHY

A lower power 25Gb/s 16:1 multiplexer using 65nm CMOS technology for 400Gb/s Ethernet (400GbE) physical layer (PHY) interface was presented. CMOS+CML mixed logic is adopted to achieve hierarchical architecture, avoiding the high clock requirement of one-step structure and improving the transmission speed. In order to reduce power while achieving high data rate, multiplexing structure is also optimized by utilizing multi-frequency multi-phase technology which not only ensures the requirement of the phase stabilization, but also leaves out some flip-flops. For CMOS-CML conversion circuit, transmission gate and cross-coupled CMOS inverter are used to match the delay of CMOS inverter, suppressing the effect of common-mode noise. Simulation results show that the multiplexer works correctly and jitter of output signal is less than 0.1UI. When voltage is 1.2V, the total power is 32.7mW at 25Gb/s.

Phase diagram studies for the growth of (Mg,Zr):SrGa12O19 crystals

By differential thermal analysis, a concentration field suitable for the growth of Zr, Mg co-doped strontium hexagallate crystals was observed that corresponds well with known experimental results. It was shown that the melting point of doped crystal is ca. 60 K higher than that of undoped crystals. This higher melting points indicate hexagallate phase stabilization by Zr, Mg co-doping and increase the growth window of (Mg,Zr):SrGa12O19, compared to undoped SrGa12O19 that grows from SrO–Ga2O3 melts.