Electrical Properties of Silicon Nanowires Schottky Barriers Prepared by MACE at Different Etching Time

Silicon ◽  
2021 ◽  
Author(s):  
Ahlem Rouis ◽  
Neila Hizem ◽  
Mohamed Hassen ◽  
Adel Kalboussi
Keyword(s):  
Electrical Properties ◽  
Silicon Nanowires ◽  
Schottky Barriers ◽  
Etching Time

scholarly journals Electrical Properties of Silicon Nanowires Schottky Barriers Prepared by MACE at Different Etching Time

2021 ◽  
Author(s):  
Ahlem Rouis ◽  
Neila Hizem ◽  
Mohamed Hassen ◽  
Adel kalboussi
Keyword(s):  
Electrical Properties ◽  
Silicon Nanowires ◽  
Thermionic Emission ◽  
Electrical Characterization ◽  
Tunneling Current ◽  
Electrical Measurement ◽  
Schottky Barriers ◽  
Etching Time ◽  
Current Voltage ◽  
Thermionic Field Emission

Abstract This article focused on the electrical characterization of silicon nanowires Schottky barriers following structural analysis of nanowires grown on p-type silicon by Metal (Ag) Assisted Chemical Etching (MACE) method distinguished by their different etching time (5min, 10min, 25min). The SiNWs are well aligned and distributed almost uniformly over the surface of a silicon wafer. In order to enable electrical measurement on the silicon nanowires device, Schottky barriers were performed by depositing Al on the vertically aligned SiNWs arrays. The electrical properties of the resulting Al/SiNWs diodes were characterized by current voltage (I-V) and capacity voltage (C-V) measurements. Unlike the conventional Schottky diode, symmetrical current-voltage (I-V) characteristics have been observed with a rectification ratio < 4. The metal-semiconductor-metal (M-S-M) model was used to analyze the (I-V) characteristics by including two Schottky barriers at the interface between metal and SiNWs. The electron transport behavior is explained by the thermionic field emission method (TFE) which added the effect of the tunneling current compared to the conventional thermionic emission theory. The capacitance-voltage C-V characteristics of SiNWs depend on the bias voltage showing that the samples have an obvious space charge region. Symmetric behavior also appears in the C –V curves that confirm the MSM model.

scholarly journals Elucidating the Effect of Etching Time Key-Parameter toward Optically and Electrically-Active Silicon Nanowires

Nanomaterials ◽  
2020 ◽  
Vol 10 (3) ◽  
pp. 404 ◽  
Author(s):  
Mariem Naffeti ◽  
Pablo Aitor Postigo ◽  
Radhouane Chtourou ◽  
Mohamed Ali Zaïbi
Keyword(s):  
Electrical Properties ◽  
Silicon Nanowires ◽  
Thermionic Emission ◽  
Cost Effective ◽  
Etching Time ◽  
Optical And Electrical Properties ◽  
Light Emitting ◽  
Excitation Volume ◽  
Silicon Nanocrystallites ◽  
Vertically Aligned

In this work, vertically aligned silicon nanowires (SiNWs) with relatively high crystallinity have been fabricated through a facile, reliable, and cost-effective metal assisted chemical etching method. After introducing an itemized elucidation of the fabrication process, the effect of varying etching time on morphological, structural, optical, and electrical properties of SiNWs was analysed. The NWs length increased with increasing etching time, whereas the wires filling ratio decreased. The broadband photoluminescence (PL) emission was originated from self-generated silicon nanocrystallites (SiNCs) and their size were derived through an analytical model. FTIR spectroscopy confirms that the PL deterioration for extended time is owing to the restriction of excitation volume and therefore reduction of effective light-emitting crystallites. These SiNWs are very effective in reducing the reflectance to 9–15% in comparison with Si wafer. I–V characteristics revealed that the rectifying behaviour and the diode parameters calculated from conventional thermionic emission and Cheung’s model depend on the geometry of SiNWs. We deduce that judicious control of etching time or otherwise SiNWs’ length is the key to ensure better optical and electrical properties of SiNWs. Our findings demonstrate that shorter SiNWs are much more optically and electrically active which is auspicious for the use in optoelectronic devices and solar cells applications.

Contacting Diffusion with FIB for Backside Circuit Edit—Procedures and Material Analysis

2005 ◽  
Author(s):  
U. Kerst ◽  
P. Sadewater ◽  
R. Schlangen ◽  
C. Boit ◽  
R. Leihkauf ◽  
...  
Keyword(s):  
Numerical Simulation ◽  
Electrical Properties ◽  
Process Parameters ◽  
Thermal Effects ◽  
Silicon Surface ◽  
Ohmic Contacts ◽  
Ion Beam ◽  
Schottky Barriers ◽  
Material Analysis ◽  
Type Silicon

Abstract The feasibility of low-ohmic FIB contacts to silicon with a localized silicidation was presented at ISTFA 2004 [1]. We have systematically explored options in contacting diffusions with FIB metal depositions directly. A demonstration of a 200nm x 200nm contact on source/drain diffusion level is given. The remaining article focuses on the properties of FIB deposited contacts on differently doped n-type Silicon. After the ion beam assisted platinum deposition a silicide was formed using a forming current in two configurations. The electrical properties of the contacts are compared to furnace anneal standards. Parameters of Schottky-barriers and thermal effects of the formation current are studied with numerical simulation. TEM images and material analysis of the low ohmic contacts show a Pt-silicide formed on a silicon surface with no visible defects. The findings indicate which process parameters need a more detailed investigation in order to establish values for a practical process.

Controlling the Size of Interior Core of Silicon Nanowires

2017 ◽  
Vol 45 ◽  
pp. 193-198 ◽  
Author(s):  
Ankur Soam ◽  
Rajiv Dusane
Keyword(s):  
Electrical Properties ◽  
Silicon Nanowires ◽  
Thermal Evaporation ◽  
Silicon Film ◽  
Chemical Vapor ◽  
Hot Wire ◽  
Vapor Liquid Solid ◽  
Thermal Evaporation Method ◽  
Evaporation Method ◽  
Template Size

As the physical and electrical properties of silicon nanowires (SiNWs) are determined by their dimension, it is necessary to control their dimension to integrate them in a device. SiNWs were synthesized via Vapor-Liquid-Solid (VLS) mechanism in hot-wire chemical vapor process (HWCVP) technique using silane as a Si source and Sn as a catalyst. Different sizes of nano-template have been made by depositing of different amount of Sn using thermal evaporation method. The size of nano-template is found to be increased with the quantity of Sn. The diameter of resulted SiNWs depends on the size of the nano-template and it increases with the nano-template size. However, the diameter of SiNWs is found to be much larger than the used nano-template which is due to the deposition of silicon film on the sidewalls of the growing SiNWs. It is demonstrated here that the diameter of the interior core of SiNWs can be controlled desirable by adjusting the size of the nano-template.

scholarly journals Fabrication of (ZnO)x: (Cu)1-x/PSi Solar Cell Using Laser Induced Plasma Technique

2021 ◽  
Vol 2114 (1) ◽  
pp. 012028
Author(s):  
G. H. Jihad ◽  
K.A. Aadim
Keyword(s):  
Solar Cell ◽  
Electrical Properties ◽  
Current Density ◽  
Electrochemical Etching ◽  
Average Diameter ◽  
Etching Process ◽  
Morphological Properties ◽  
Etching Time ◽  
Solar Cell Performance ◽  
Cell Efficiency

Abstract Fabrication of PSi is generated successfully depending upon photo-electrochemical etching process. The purpose is to differentiate the characterization of the PSi monolayer based on c-silicon solar cell compared to the bulk silicon alone. The surface of ordinary p-n solar cell has been reconstructed on the n-type region of (100) orientation with resistivity (3.2.cm) in hydrofluoric (HF) acid at a concentration of 2 ml was used to in order to enhance the conversion efficiency with 10-minute etching time and current density of 50 mA/cm2, The morphological properties (AFM) as well as the electrical properties have been investigated (J-V). The atomic force microscopy investigation reveals a rugged silicon surface with porous structure nucleating during the etching process (etching time), resulting in an expansion in depth and an average diameter of (40.1 nm). As a result, the surface roughness increases. The electrical properties of prepared PS, namely current density-voltage characteristics in the dark, reveal that porous silicon has a sponge-like structure and that the pore diameter increases with increasing etching current density and the number of shots increasing this led that the solar cell efficiency was in the range of (1-2%), resulting in improved solar cell performance.

Synthesis of Silicon Nanowire Arrays by Metal-Assisted Chemical Etching in Aqueous NH4HF2 Solution

2012 ◽  
Vol 21 ◽  
pp. 109-115 ◽  
Author(s):  
S. Naama ◽  
T. Hadjersi ◽  
G. Nezzal ◽  
L. Guerbous
Keyword(s):  
Silicon Nanowires ◽  
Chemical Etching ◽  
Silicon Nanowire ◽  
Nanowire Arrays ◽  
Etching Time ◽  
Silicon Nanowire Arrays ◽  
Peak Intensity ◽  
One Step ◽  
Etching Parameters ◽  
P Type

One-step metal-assisted electroless chemical etching of p-type silicon substrate in NH4HF2/AgNO3 solution was investigated. The effect of different etching parameters including etching time, temperature, AgNO3 concentration and NH4HF2 concentration were investigated. The etched layers formed were investigated by scanning electron microscopy (SEM) and Photoluminescence. It was found that the etched layer was formed by well-aligned silicon nanowires. It is noted that their density and length strongly depend on etching parameters. Room temperature photoluminescence (PL) from etched layer was observed. It was observed that PL peak intensity increases significantly with AgNO3 concentration.

Reactive Ion Etching Damage to Ferroelectric Thin Films Capacitors

1994 ◽  
Vol 361 ◽  
Author(s):  
W. Pan ◽  
C.L. Thio ◽  
S.B. Desu ◽  
Cheewon Chung
Keyword(s):  
Thin Films ◽  
Electrical Properties ◽  
Leakage Current ◽  
Reactive Ion Etching ◽  
Ferroelectric Thin Films ◽  
Electric Properties ◽  
Etching Time ◽  
Ion Etching ◽  
Before And After ◽  
Ferroelectric Capacitors

ABSTRACTReactive ion etching damage to sputtered Pt/PZT/Pt ferroelectric capacitors was studied using Ar and CHCIFCF3 etch gases. Electrical properties, hysteresis, fatigue, and leakage current of PZT capacitors, before and after etching, were compared to examine the etching damage. It is found that the damage effects depend on etching time and are mainly due to the physical bombardment effect. The PZT capacitors etched with CHCIFCF3 plasma showed less damage than those etched in Ar plasma. The electric properties of etched Pt/PZT/Pt capacitors are recovered by annealing at 400 °C for 30min.

scholarly journals Fabrication and Photovoltaic Characteristics of Coaxial Silicon Nanowire Solar Cells Prepared by Wet Chemical Etching

2012 ◽  
Vol 2012 ◽  
pp. 1-8 ◽  
Author(s):  
Chien-Wei Liu ◽  
Chin-Lung Cheng ◽  
Bau-Tong Dai ◽  
Chi-Han Yang ◽  
Jun-Yuan Wang
Keyword(s):  
Solar Cells ◽  
Silicon Nanowires ◽  
Chemical Etching ◽  
Low Cost ◽  
Light Trapping ◽  
Silicon Nanowire ◽  
Great Promise ◽  
Etching Time ◽  
Wet Chemical ◽  
Wet Chemical Etching

Nanostructured solar cells with coaxial p-n junction structures have strong potential to enhance the performances of the silicon-based solar cells. This study demonstrates a radial junction silicon nanowire (RJSNW) solar cell that was fabricated simply and at low cost using wet chemical etching. Experimental results reveal that the reflectance of the silicon nanowires (SNWs) declines as their length increases. The excellent light trapping was mainly associated with high aspect ratio of the SNW arrays. A conversion efficiency of ∼7.1% and an external quantum efficiency of ∼64.6% at 700 nm were demonstrated. Control of etching time and diffusion conditions holds great promise for the development of future RJSNW solar cells. Improving the electrode/RJSNW contact will promote the collection of carries in coaxial core-shell SNW array solar cells.

scholarly journals A Facile, Low-Cost Plasma Etching Method for Achieving Size Controlled Non-Close-Packed Monolayer Arrays of Polystyrene Nano-Spheres

Nanomaterials ◽  
2019 ◽  
Vol 9 (4) ◽  
pp. 605 ◽  
Author(s):  
Yun Chen ◽  
Dachuang Shi ◽  
Yanhui Chen ◽  
Xun Chen ◽  
Jian Gao ◽  
...  
Keyword(s):  
Plasma Etching ◽  
Silicon Nanowires ◽  
High Frequency ◽  
Low Cost ◽  
Etching Rate ◽  
Low Frequency ◽  
Etching Time ◽  
High Frequency Plasma ◽  
Frequency Plasma ◽  
Etching System

Monolayer nano-sphere arrays attract great research interest as they can be used as templates to fabricate various nano-structures. Plasma etching, and in particular high-frequency plasma etching, is the most commonly used method to obtain non-close-packed monolayer arrays. However, the method is still limited in terms of cost and efficiency. In this study, we demonstrate that a low frequency (40 kHz) plasma etching system can be used to fabricate non-close-packed monolayer arrays of polystyrene (PS) nano-spheres with smooth surfaces and that the etching rate is nearly doubled compared to that of the high-frequency systems. The study reveals that the low-frequency plasma etching process is dominated by a thermal evaporation etching mechanism, which is different from the atom-scale dissociation mechanism that underlines the high-frequency plasma etching. It is found that the polystyrene nano-sphere size can be precisely controlled by either adjusting the etching time or power. Through introducing oxygen as the assisting gas in the low frequency plasma etching system, we achieved a coalesced polystyrene nano-sphere array and used it as a template for metal-assisted chemical etching. We demonstrate that the method can significantly improve the aspect ratio of the silicon nanowires to over 200 due to the improved flexure rigidity.

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