scholarly journals A 1.8V 1.1-GHZ Novel 8 X 8-Bit Digital Multiplier

2021 ◽  
Author(s):  
Amir Ali Khatibzadeh
Keyword(s):  
High Performance ◽  
Linear Array ◽  
Full Adder ◽  
System Level ◽  
Power Performance ◽  
Circuit Realization ◽  
Silicon Area ◽  
Multiplication Algorithm ◽  
Parallel Addition ◽  
The Common

This thesis presents the design of an 8x8-bit novel multiplier, which can provide a better performance that its counterparts in the sense that it has a fraction of the silicon area, delay and power consumption of the common architectures such as the conventional linear array multipliers. At the system-level high performance is obtained by implementing a pair-wise multiplication algorithm. Also, parallel addition algorithm is used to add up partial products. Combining these two algorithms results in an efficient cell-based circuit realization. In the circuit-level, pseudo-NMOS full adder cell is chosen amongst the several existing full adder cells due to its superior speed and power performance. The performance of this design has been evaluated by comparing it to those of the recently reported multipliers. The results of the comparison, both in theory and simulation, prove the superiority of the proposed multiplier.

scholarly journals A 1.8V 1.1-GHZ Novel 8 X 8-Bit Digital Multiplier

2021 ◽  
Author(s):  
Amir Ali Khatibzadeh
Keyword(s):  
High Performance ◽  
Linear Array ◽  
Full Adder ◽  
System Level ◽  
Power Performance ◽  
Circuit Realization ◽  
Silicon Area ◽  
Multiplication Algorithm ◽  
Parallel Addition ◽  
The Common

This thesis presents the design of an 8x8-bit novel multiplier, which can provide a better performance that its counterparts in the sense that it has a fraction of the silicon area, delay and power consumption of the common architectures such as the conventional linear array multipliers. At the system-level high performance is obtained by implementing a pair-wise multiplication algorithm. Also, parallel addition algorithm is used to add up partial products. Combining these two algorithms results in an efficient cell-based circuit realization. In the circuit-level, pseudo-NMOS full adder cell is chosen amongst the several existing full adder cells due to its superior speed and power performance. The performance of this design has been evaluated by comparing it to those of the recently reported multipliers. The results of the comparison, both in theory and simulation, prove the superiority of the proposed multiplier.

scholarly journals High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

2021 ◽  
pp. 263-269
Author(s):  
Tejaswini M. L ◽  
Aishwarya H ◽  
Akhila M ◽  
B. G. Manasa
Keyword(s):  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Power Performance ◽  
High Speed Design ◽  
Power Delay Product ◽  
Full Swing ◽  
Output Swing ◽  
High Output

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

High-performance light trajectory tracking and image sensing devices based on a γ-In2Se3/GaAs heterostructure

2020 ◽  
Vol 8 (39) ◽  
pp. 13762-13769
Author(s):  
Jing-Wei Kang ◽  
Chao Zhang ◽  
Kai-Jun Cao ◽  
Yu Lu ◽  
Chun-Yan Wu ◽  
...  
Keyword(s):  
Real Time ◽  
Trajectory Tracking ◽  
High Performance ◽  
Linear Array ◽  
Image Sensing ◽  
Optoelectronic Applications

A high-performance γ-In2Se3/GaAs heterostructure-based photodetector linear array shows potential in optoelectronic applications such as real-time light trajectory tracking and image sensing.

scholarly journals Fast Comparison of High-Precision Time Scales Using GNSS Receivers

2017 ◽  
Vol 2017 ◽  
pp. 1-4
Author(s):  
Vojtech Vigner ◽  
Jaroslav Roztocil
Keyword(s):  
Time Scales ◽  
Time Scale ◽  
High Performance ◽  
Data Format ◽  
Common View ◽  
Log Files ◽  
Gnss Receivers ◽  
Precision Time ◽  
The Common ◽  
The Difference

Comparison of high-performance time scales generated by atomic clocks in laboratories of time and frequency metrology is usually performed by means of the Common View method. Laboratories are equipped with specialized GNSS receivers which measure the difference between a local time scale and a time scale of the selected satellite. Every receiver generates log files in CGGTTS data format to record measured differences. In order to calculate time differences recorded by two receivers, it is necessary to obtain these logs from both receivers and process them. This paper deals with automation and speeding up of these processes.

scholarly journals 2 + 1 Highways: Overview and Future Directions

2018 ◽  
Vol 2018 ◽  
pp. 1-13
Author(s):  
Manuel Romana ◽  
Marilo Martin-Gasulla ◽  
Ana T. Moreno
Keyword(s):  
Urban Areas ◽  
High Performance ◽  
White Paper ◽  
Future Directions ◽  
Research Directions ◽  
Traffic Volumes ◽  
Primary Means ◽  
The Common ◽  
Rural Access ◽  
Transportation Research

Most of the rural transportation system is composed of two-lane highways, and many of them serve as the primary means for rural access to urban areas and freeways. In some highways, traffic volumes can be not high enough to justify a four-lane highway but higher than can be served by isolated passing lanes, or can present high number of head-on collisions. In those conditions, 2 + 1 highways are potentially applicable. This type of highway is used to provide high-performance highways as intermediate solution between the common two-lane highway and the freeway. Successful experiences reported in Germany, Sweden, Finland, Poland, or Texas (US) may suggest that they are potentially applicable in other countries. The objective of this white paper is to provide an overview of the past practice in 2 + 1 highways and discuss the research directions and challenges in this field, specially focusing on, but not limited to, operational research in association with the activities of the Subcommittee on Two-Lane Highways (AHB40 2.2) of the Transportation Research Board. The significance of this paper is twofold: (1) it provides wider coverage of past 2 + 1 highways design and evaluation, and (2) it discusses future directions of this field.

Prediction: The Modern-Day Sport-Science and Sports-Medicine “Quest for the Holy Grail”

2017 ◽  
Vol 12 (5) ◽  
pp. 704-706 ◽  
Author(s):  
Alan McCall ◽  
Maurizio Fanchini ◽  
Aaron J. Coutts
Keyword(s):  
Sports Medicine ◽  
High Performance ◽  
Psychological Tests ◽  
Screening Tools ◽  
Holy Grail ◽  
Sport Science ◽  
The Common ◽  
Injury Screening

In high-performance sport, science and medicine practitioners employ a variety of physical and psychological tests, training and match monitoring, and injury-screening tools for a variety of reasons, mainly to predict performance, identify talented individuals, and flag when an injury will occur. The ability to “predict” outcomes such as performance, talent, or injury is arguably sport science and medicine’s modern-day equivalent of the “Quest for the Holy Grail.” The purpose of this invited commentary is to highlight the common misinterpretation of studies investigating association to those actually analyzing prediction and to provide practitioners with simple recommendations to quickly distinguish between methods pertaining to association and those of prediction.

Design and synthesis of hierarchical mesoporous WO3-MnO2 composite nanostructures on carbon cloth for high-performance supercapacitors

2017 ◽  
Vol 3 (1) ◽  
Author(s):  
Pragati A. Shinde ◽  
Vaibhav C. Lokhande ◽  
Amar M. Patil ◽  
Taeksoo Ji ◽  
Chandrakant D. Lokhande
Keyword(s):  
Energy Density ◽  
High Performance ◽  
Rational Design ◽  
Electrode Materials ◽  
Mesoporous Structure ◽  
Carbon Cloth ◽  
Power Performance ◽  
Active Electrode ◽  
Composite Nanostructures ◽  
Design And Synthesis

AbstractTo enhance the energy density and power performance of supercapacitors, the rational design and synthesis of active electrode materials with hierarchical mesoporous structure is highly desired. In the present work, fabrication of high-performance hierarchical mesoporous WO

scholarly journals A High-Performance Skin Impedance Measurement Circuit for Biomedical Applications

2019 ◽  
Vol 28 (07) ◽  
pp. 1950110 ◽  
Author(s):  
K. Hayatleh ◽  
S. Zourob ◽  
R. Nagulapalli ◽  
S. Barker ◽  
N. Yassine ◽  
...  
Keyword(s):  
Biomedical Applications ◽  
High Performance ◽  
Impedance Measurement ◽  
Cmos Technology ◽  
Skin Impedance ◽  
Instrumentation Amplifier ◽  
Measurement Circuit ◽  
Silicon Area ◽  
The Impact ◽  
Mode Interference

This paper describes a high-performance impedance measurement circuit for the application of skin impedance measurement in the early detection of skin cancer. A CMRR improvement technique has been adopted for OTAs to reduce the impact of high-frequency common mode interference. A modified three-OTA instrumentation amplifier (IA) has been proposed to help with the impedance measurement. Such systems offer a quick, noninvasive and painless procedure, thus having considerable advantages over the currently used approach, which is based upon the testing of a biopsy sample. The sensor has been implemented in 65[Formula: see text]nm CMOS technology and post-layout simulations confirm the theoretical claims we made and sensor exhibits sensitivity. Circuit consumes 45[Formula: see text]uW from 1.5[Formula: see text]V power supply. The circuit occupies 0.01954[Formula: see text]mm2 silicon area.

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