scholarly journals Analysis of Low Power Dynamic Comparator

2020 ◽  
Vol 9 (7) ◽  
pp. 329-332
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Low Power Consumption ◽  
Performance Parameters ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Static Power ◽  
Dynamic Comparators

Low power consumption, high performance dynamic comparators are widely used in high-speed Analog to Digital Converters (ADCs) and advanced input/output circuits. Mostly unique comparators utilize the latching stage thorough cross-coupled inverters, which gives a solid positive feedback, to fasten the comparison and reduce the static- power dissipation. In this paper, the analysis of dynamic comparators having best performance parameters in terms of power dissipation is presented. This is achieved by adopting low power techniques like adding transistors and sizing them to get efficient circuit. The proposed circuits are able to reduce power dissipation from 40-50%

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

Design of Low Power CMOS Comparator using 180nm Technology for ADC Application

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 11-13
Author(s):  
Truptimayee Behera ◽  
Ritisnigdha Das
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Input Voltage ◽  
Clock Frequency ◽  
Nmos Transistor ◽  
Body Effect ◽  
Low Power Dissipation ◽  
Low Power Cmos

In our design of CMOS comparator with high performance using GPDK 180nm technology we optimize these parameters. We analyse the transient response of the schematic design and the gain is calculated in AC analysis and also we measure the power dissipation. The circuit is built by using PMOS and NMOS transistor with a body effect. A plot of phase and gain also discussed in the paper. Finally a test schematic is built and transient analysis for an input voltage of 2V is measured using Cadence virtuoso. Simulation results are presented and it shows that this design can work under high speed clock frequency 200MHz. The design has low power dissipation.

Low-power consumption seamless wireless and wired links using transparent waveform transfer

2014 ◽  
Vol 3 (5-6) ◽  
Author(s):  
Tetsuya Kawanishi
Keyword(s):  
Power Consumption ◽  
Optical Fiber ◽  
Low Power ◽  
Millimeter Wave ◽  
Optical Fibers ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Low Power Consumption ◽  
Wireless Links

AbstractThis paper describes wired and wireless seamless networks consisting of radiowave and optical fiber links. Digital coherent technology developed for high-speed optical fiber transmission can mitigate signal deformation in radiowave links in the air as well as in optical fibers. Radio-over-fiber (RoF) technique, which transmits radio waveforms on intensity envelops of optical signals, can provide direct waveform transfer between optical and radio signals by using optical-to-electric or electric-to-optical conversion devices. Combination of RoF in millimeter-wave bands and digital coherent with high-performance digital signal processing (DSP) can provide wired and wireless seamless links where bit rate of wireless links would be close to 100 Gb/s. Millimeter-wave transmission distance would be shorter than a few kilometers due to large atmospheric attenuation, so that many moderate distance wireless links, which are seamlessly connected to optical fiber networks should be required to provide high-speed mobile-capable networks. In such systems, reduction of power consumption at media converters connecting wired and wireless links would be very important to pursue both low-power consumption and large capacity.

Thermometer to Gray Encoders

2015 ◽  
pp. 323-335
Author(s):  
Yogendra Gupta ◽  
Sandeep Saini
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Gray Code ◽  
Direct Conversion ◽  
Flash Adc ◽  
Analog To Digital ◽  
Modulation Techniques ◽  
On Chip ◽  
Minimal Area

Analog to Digital Converter (ADC) is a key functional block in the design of mixed signal, system on chip, and signal processing applications. An optimized method for the direct conversion of analog signal to Gray code representation is presented. This eliminates the need for binary-to-Gray code conversion in many digital modulation techniques like M-PSK and M-QAM, which uses Gray coding representation to represent the symbols that are modulated. The authors design a low-power and high-speed Thermometer to Gray encoder for Flash ADC, as encoders have been widely utilized in high-performance critical applications which persistently impose special design constraints in terms of high-frequency, low power consumption, and minimal area. In this chapter, they propose a new circuit that converts the Thermometer code to Gray code and also yields minimized power.

scholarly journals A Low Power, High Speed 1.2 V Dynamic Comparator for Analog-to-Digital Converters

2020 ◽  
Vol 171 ◽  
pp. 1018-1026
Author(s):  
Sahil Jakhar ◽  
Vishal Singh Mandloi ◽  
Rupam Goswami ◽  
Kavindra Kandpal
Keyword(s):  
Low Power ◽  
High Speed ◽  
Analog To Digital Converters ◽  
Dynamic Comparator ◽  
Analog To Digital

AN OPTIMIZED LOW POWER PIPELINE ANALOG-TO-DIGITAL CONVERTER FOR HIGH-SPEED WLAN APPLICATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450059 ◽  
Author(s):  
MAO YE ◽  
BIN WU ◽  
YONGXU ZHU ◽  
YUMEI ZHOU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Dynamic Range ◽  
Cmos Process ◽  
Area Network ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Silicon Area ◽  
Analog To Digital

This paper presents the design and implementation of a 11-bit 160 MSPS analog-to-digital converter (ADC) for next generation super high-speed wireless local area network (WLAN) application. The ADC core consists of one front sample and hold stage and four cascades of 2.5 bit pipeline stages with opamp sharing between successive stages. To achieve low power dissipation at 1.2 V supply, a single stage symmetrical amplifier with double transimpedance gain-boosting amplifier is proposed. High speed on-chip reference buffer with replica source follower is also included for linearity performance. The ADC was fabricated in a standard 130-nm CMOS process and an occupied silicon area of 0.95 mm × 1.15 mm. Performance of 73 dB spurious-free-dynamic-range is measured at 160 MS/s with 1 Vpp input signal. The power dissipation of the analog core chip is only 50 mW from a 1.2 V supply.

Analytical Study Of Full Adder Circuit Using Modified Glitch Free Cascadable Adiabatic Logic

2018 ◽  
Vol 3 (2) ◽  
Author(s):  
Neha Raghav ◽  
◽  
Malti Bansal
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Performance ◽  
Analytical Study ◽  
Supply Voltage ◽  
Full Adder ◽  
Vlsi Circuits ◽  
Low Power Consumption ◽  
Adiabatic Logic

Nowadays, power dissipation is among the most dominant concerns in designing a VLSI circuits. Endless improvement in technology has points to an increased requirement for devices which have the basic characteristic of low power consumption. Hence power has turn into a demanding design parameter in low power and high-performance applications. The Adiabatic logic technique is becoming a solution to the dilemma of power dissipation. Adders with huge power consumption affect the overall efficiency of the system. Hence, in this paper, the proposed application of full adder circuit is shown using the Modified Glitch Free Cascadable Adiabatic Logic. The circuit is compared with the conventional CMOS Logic and the power dissipation analysis is simulated with supply voltage = 0.9 V, 1.2 V and 1.8 V to analyze the pattern followed with supply variation at different temperature range. Similarly, the calculation of delay is performed for temperature values of 27˚C, 55˚C and 120˚C at 90nm technology.

scholarly journals A 5 Bit 600MS/S Asynchronous Digital Slope ADC with Modified Strong Arm Comparator

2019 ◽  
Vol 9 (1S5) ◽  
pp. 41-44
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Average Power ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Delay Cell ◽  
Offset Voltage ◽  
Static Power ◽  
Cell Sample ◽  
Low Offset

Strong arm comparator has some characteristics like it devours zero static power and yields rail to rail swing. It acquires a positive feedback allowed by two cross coupled pairs of comparators and results a low offset voltage in input differential stage. We modified a strong arm Comparator for high speed without relying on complex calibration Schemes. a 5- bit 600MS/s asynchronous digital slope analog to digital converter (ADS-ADC) with modified strong arm comparator designed in cadence virtuoso at 180nm CMOS technology. The design of SR-Latch using Pseudo NMOS NOR Gate optimizes the speed. Thus delay reduced in select signal generation block. Power dissipation is minimized with lesser transistor count in Strong arm comparator and SR-Latch with maximum sampling speed. The speed of the converter can be improved by resolution. The proposed circuit is 5-bit ADC containing a delay cell, Sample and hold, continuous time comparator, strong arm comparator, Pseudo NMOS SR-Latch and Multiplexer. This 5- bit ADC operates voltage at 1.8 volts and consumes an average power.

scholarly journals Realization of Various Topologies of Adders Based on H-Dycml

2020 ◽  
Vol 9 (4) ◽  
pp. 1865-1891
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Current Mode ◽  
Cmos Technology ◽  
Performance Parameters ◽  
Current Mode Logic ◽  
Look Ahead ◽  
Overall Performance ◽  
Power Delay Product

Power consumption minimization in a circuit becomes imperative with growth in demands of portable goods. However, at the same time, its speed limits the performance of a system. Therefore, there is a need of choosing optimum circuit architecture that takes into account the both conflicting parameters, that is, power dissipation and speed. Arithmetic unit is one of the vital components of portable goods and out of all arithmetic operations, adders are the most commonly used. To address the issue of high power dissipation, low-power designing styles are becoming prominent now-a-days. Hybrid Dynamic Current Mode Logic is high-speed, low-power designing style that has been recently proposed in literature. Therefore, this paper presents the comparison between performances of various topologies of adders that are implemented using a high-speed, low-power designing style: Hybrid-Dynamic Current Mode Logic (H-DyCML). All the circuits are realized in Cadence Virtuoso using 180nm CMOS technology parameter. Various performance parameters are evaluated such as: Delay, Power, Power-Delay Product, and hardware utilization. It is found that carry look-ahead adder out-stands other adders in terms of overall performance.

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