Deformation Behavior of Various Interconnection Structures Using Fine Pitch Microelectromechanical Systems (MEMS) Vertical Probe

Recently, fine pitch wafer level packaging (WLP) technologies have drawn a great attention in the semiconductor industries. WLP technology uses various interconnection structures including microbumps and through-silicon-vias (TSVs). To increase yield and reduce cost, there is an increasing demand for wafer level testing. Contact behavior between probe and interconnection structure is a very important factor affecting the reliability and performance of wafer testing. In this study, with a MEMS vertical probe, we performed systematic numerical analysis of the deformation behavior of various interconnection structures, including solder bump, copper (Cu) pillar bump, solder capper Cu bump, and TSV. During probing, the solder ball showed the largest deformation. The Cu pillar bump also exhibited relatively large deformation. The Cu bump began to deform at OD of 10 μm. At OD of 20 μm, bump pillar was compressed, and the height of the bump decreased by 8.3%. The deformation behavior of the solder capped Cu bump was similar to that of the solder ball. At OD of 20 μm, the solder and Cu bumps were largely deformed, and the total height was reduced by 11%. The TSV structure showed the lowest deformation, but exerted the largest stress on the probe. In particular, copper protrusion at the outer edge of the via was observed, and very large shear stress was generated between the via and the silicon oxide layer. In summary, when probing various interconnection structures, the probe stress is less than that when using an aluminum pad. On the other hand, deformation of the structure is a critical issue. In order to minimize damage to the interconnection structure, smaller size probes or less overdrive should be used. This study will provide important guidelines for performing wafer-level testing and minimizing damage of probes and interconnection structures.

Inhibiting Effects of the Ni Barrier Layer on the Growth of Porous Cu3sn in 10 μm Microbumps

With the shrinkage of size, porous Cu3Sn have become a new potential threat of the reliability in micron Cu pillar bump. The formation of porous Cu3Sn is contributed the decomposition of Cu6Sn5, which is caused by the overgrowth of intermetallic compounds (IMC) and the stress introduced by the phase transition of Cu6Sn5. In this paper, uniform Ф10 µm Cu/Sn and Cu/Ni (~0.6 μm)/Sn microbumps have been fabricated by multilayer electrodeposition and the effect of the Ni layer on the growth behavior of porous Cu3Sn was investigated by comparing the evolution of IMC in Cu/Sn and Cu/Ni/Sn bumps aged at 170 ℃ and 200 ℃. The ~0.6 μm Ni layer can effectively retard the Cu atoms diffusion, which can hinder IMC from overgrowth. Moreover, with the help of X-ray diffraction (XRD), the ability of the Ni layer in stabilizing Cu6Sn5 phase is strengthened, which weakens the tendency of the porous Cu3Sn formation. Under the conjoint action of retarding the growth of IMC and stabilizing Cu6Sn5 phase, the Ni layer can inhibit the formation of porous Cu3Sn efficaciously.

Bumping Co-planarity Collocation for Different UBM Size by Geometry Integration

Bumping co-planarity is a Cu pillar bump characteristic, that can impact to the joint quality of subsequent flip chip bonding process. The plated bump height variation correlates with lesser co-planarity values. Co-planarity can be minimized by bumping process, however the bumping process window is not adequate for some design features. For example, dummy bump or structure drawback features. This paper provides a methodology to improve co-planarity by collocating oval and circular bump which integrates the solder volume of different bump shapes. The final solder formation is different due to the geometry variation from the oval shape and circular shape. The final solder height can be calculated by mathematical integral from as-plated solder volume. Hence, better co-planarity can be achieved by the proposed method to collocate different bump shapes. The Cu pillar bump collocation design rules can be optimized to minimize co-planarity during initial design realization to minimize quality risks during fabrication..

Special Sample Preparation Methodology for Cu Pillar Bump Characterization on Advance Thin Small Leadless Flip Chip with Copper Pillar Bump Interconnect Technology

Today, copper pillar bumping now in high volume production for mobile electronics is also a transformative technology for next generation flip chip [1] interconnects which offers advantages in many designs while meeting current and future requirements. With the continuous shrinking dimensions of semiconductor devices, the package’s design and size are approaching the dimensions of the singulated die. Moreover, failure analysis involving copper pillar packages would be the major challenges faced by analysts as copper pillar devices in nature hides its solder joints beneath its die causing obstruction in quality inspection as well as judging its solder joint strength. Chemical wet etch or deprocessing [2] by using potassium hydroxide (KOH) to remove all silicon die have disadvantages of over etching on silicon substrate and tin (Sn) surrounding the Cu pillar. Therefore, quality of sample preparation is critical and new methodology is needed.