scholarly journals Device Simulation of The GeSe Homojunction And vdW GeSe/GeTe Heterojunction TFETs For High-Performance Application

2021 ◽  
Author(s):  
Qida Wang ◽  
Peipei Xu ◽  
Hong Li ◽  
Fengbin Liu ◽  
Shuai Sun ◽  
...  
Keyword(s):  
Ab Initio ◽  
Quantum Transport ◽  
Delay Time ◽  
High Performance ◽  
Device Simulation ◽  
Promising Method ◽  
Tunneling Barrier ◽  
High Performance Application ◽  
Power Delay Product ◽  
Source Use

Abstract Compared with a 2D homogeneous channel, the introduction of a 2D/2D homojunction or heterojunction is a promising method to promote the performance of a TFET mainly by controlling the tunneling barrier. We simulate the 10-nm-Lg double-gated GeSe homojunction TFETs and vdW GeSe/GeTe heterojunction TFETs using the ab initio quantum transport calculations. Two constructions are considered for both the homojunction and heterojunction TFETs by placing the BL GeSe and vdW GeSe/GeTe heterojunction as the source or drain while the channel and the remaining drain or source use ML GeSe. The on-state current (Ion) of the optimal n-type BL-ML GeSe source homojunction TFET and the optimal p-type vdW GeSe/GeTe drain heterojunction TFET are 2320 and 2387 μA μm-1, respectively, which are 50% and 64% larger than Ion of the ML GeSe homogeneous TFET. Inspiringly, the device performances (Ion, intrinsic delay time τ, and power delay product PDP) of both the optimal n-type GeSe homojunction and p-type vdW GeSe/GeTe heterojunction TFETs meet the requirement of the International Roadmap for Device and Systems high-performance device for the year of 2034 (2020 version).

Quantum transport simulation of the two-dimensional GaSb transistors

2021 ◽  
Vol 42 (12) ◽  
pp. 122001
Author(s):  
Panpan Wang ◽  
Songxuan Han ◽  
Ruge Quhe
Keyword(s):  
Quantum Transport ◽  
Delay Time ◽  
High Performance ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Two Dimensional ◽  
Ballistic Performance ◽  
Transport Simulation ◽  
Technology Roadmap ◽  
Power Delay Product

Abstract Owing to the high carrier mobility, two-dimensional (2D) gallium antimonite (GaSb) is a promising channel material for field-effect transistors (FETs) in the post-silicon era. We investigated the ballistic performance of the 2D GaSb metal–oxide–semiconductor FETs with a 10 nm-gate-length by the ab initio quantum transport simulation. Because of the wider bandgap and better gate-control ability, the performance of the 10-nm monolayer (ML) GaSb FETs is generally superior to the bilayer counterparts, including the three-to-four orders of magnitude larger on-current. Via hydrogenation, the delay-time and power consumption can be further enhanced with magnitude up to 35% and 57%, respectively, thanks to the expanded bandgap. The 10-nm ML GaSb FETs can almost meet the International Technology Roadmap for Semiconductors (ITRS) for high-performance demands in terms of the on-state current, intrinsic delay time, and power-delay product.

scholarly journals Impact of Mole Fraction Variation on Nanoscale SiGe Hybrid FinFET on Insulator

2019 ◽  
Vol 8 (12S2) ◽  
pp. 61-66
Keyword(s):  
Band Gap ◽  
Mole Fraction ◽  
High Performance ◽  
Device Simulation ◽  
Channel Length ◽  
Gate Length ◽  
Electrical Characteristics ◽  
Simulation Results ◽  
High Performance Application ◽  
Device Modelling

This work investigates the performance of SiGe Hybrid JunctionLess FinFET (HJLFinFET) on insulator with different mole fraction x. The band gap difference for different mole fractions are explored. Impact of electrical characteristics and SCE of HJLFinFET are analyzed with fin width 10nm and varying gate length from 5nm-40nm for different mole fraction. Synopsys Sentaurus TCAD tool(sprocess and sdevice) are used in Device modelling and device simulation. Simulation results shows improvement in On current, DIBL and SS. For high performance application SiGe with mole fraction less than 0.3 at channel length less than 10nm are suitable because of the bandgap value is similar to silicon.

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 55-62
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Clock Frequency ◽  
Charge Sharing ◽  
Benchmark Circuit ◽  
Domino Circuit ◽  
Power Delay Product ◽  
Domino Circuits ◽  
Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

Direct Laser Cooling Schemes for the Triatomic SOH and SeOH Molecules Based on Ab Initio Electronic Properties

2020 ◽  
Author(s):  
Li Liu ◽  
Chuan-Lu Yang ◽  
Zhaopeng Sun ◽  
Meishan Wang ◽  
Xiano-Guang Ma
Keyword(s):  
Optical Properties ◽  
Ab Initio ◽  
Electronic Properties ◽  
Laser Cooling ◽  
Promising Method ◽  
Optical Scheme ◽  
Electronic And Optical Properties ◽  
Cold Molecules ◽  
Direct Laser

The direct laser cooling is a very promising method to obtain cold molecules for various applications. However, a molecule with satisfactory electronic and optical properties for the optical scheme is...

Selection of selective laser sintering materials for different applications

2015 ◽  
Vol 21 (6) ◽  
pp. 630-648 ◽  
Author(s):  
Sunil Kumar Tiwari ◽  
Sarang Pande ◽  
Sanat Agrawal ◽  
Santosh M. Bobade
Keyword(s):  
Process Parameters ◽  
High Performance ◽  
Material Selection ◽  
Selective Laser Sintering ◽  
Laser Sintering ◽  
Optimal Process ◽  
Content Type ◽  
Volume Production ◽  
High Performance Application ◽  
Selection Of

Purpose – The purpose of this paper is to propose and evaluate the selection of materials for the selective laser sintering (SLS) process, which is used for low-volume production in the engineering (e.g. light weight machines, architectural modelling, high performance application, manufacturing of fuel cell, etc.), medical and many others (e.g. art and hobbies, etc.) with a keen focus on meeting customer requirements. Design/methodology/approach – The work starts with understanding the optimal process parameters, an appropriate consolidation mechanism to control microstructure, and selection of appropriate materials satisfying the property requirement for specific application area that leads to optimization of materials. Findings – Fabricating the parts using optimal process parameters, appropriate consolidation mechanism and selecting the appropriate material considering the property requirement of applications can improve part characteristics, increase acceptability, sustainability, life cycle and reliability of the SLS-fabricated parts. Originality/value – The newly proposed material selection system based on properties requirement of applications has been proven, especially in cases where non-experts or student need to select SLS process materials according to the property requirement of applications. The selection of materials based on property requirement of application may be used by practitioners from not only the engineering field, medical field and many others like art and hobbies but also academics who wish to select materials of SLS process for different applications.

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