scholarly journals Enhanced Self Checking Carry Select Adder using Dynamic Logic Based Full Adder

2020 ◽  
Vol 8 (5) ◽  
pp. 1521-1525
Keyword(s):  
Dynamic Logic ◽  
Vlsi Design ◽  
Full Adder ◽  
Higher Order ◽  
The Self ◽  
Gate Circuit ◽  
Carry Select Adder ◽  
Nor Gate ◽  
Reduction In Area

Fast adders are constructed mainly by Carry select adders (CSLA). Area is one of the main concerns as far as any VLSI design is considered. In connection this paper enhances the performance of self checking carry select adder by introducing un footed dynamic logic based full adder cell instead of a regular CMOS based adders. The adder is constructed with 10 transistors based on the optimization of truth tale of a full adder. A 3 transistor X-NOR gate circuit is also used instead of a conventional X-NOR circuit in the self checking path. Adders of size 4 bit and 8 bit are constructed in various technologies. The results show that the proposed structure reduces the transistor over head by almost 47% and 46% for 4bit and 8bit structures respectively. By achieving this much of reduction in area this work could be suggested for higher order VLSI structures like BIST,DCT etc.,

scholarly journals XOR Based Carry Select Adder for Area and Delay

2020 ◽  
Vol 5 (6) ◽  
pp. 1615-1621
Author(s):  
Ramyabanu Bobba ◽  
Pooja Illa
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Design Research ◽  
Logic Gate ◽  
Vlsi Design ◽  
Full Adder ◽  
Low Area ◽  
Carry Select Adder ◽  
Technology Comparison

Low power and area proficient high-speed circuits are the most important areas in VLSI design research. Carry select adder is one of the fastest adders with the low area and power consumption. The paper introduces a 16-bit carry select adder with an optimized multiplexer based full adder circuit using Gate Diffusion Input logic (GDI) technology. Comparison is done on Area, Power and Delay parameters. Our circuit requires only two XOR gates and a multiplexer. In this, each logic gate is designed using GDI technology. This further reduces the transistor count resulting in Area, power, delay and complexity minimization. The proposed 16-bit carry select adder provides better results compared to the conventional 16-bit carry select adder with Area and delay.

Combined influence of axial electron temperature and exponential plasma density ramp on the self-focusing of a chirped laser in plasma

2020 ◽  
Vol 75 (7) ◽  
pp. 671-675
Author(s):  
Niti Kant ◽  
Vishal Thakur
Keyword(s):  
Electron Temperature ◽  
Pulse Laser ◽  
Plasma Density ◽  
Beam Width ◽  
Spot Size ◽  
Higher Order ◽  
The Self ◽  
Chirped Pulse ◽  
Self Focusing ◽  
Paraxial Ray

AbstractAn analysis of the self-focusing of highly intense chirped pulse laser under exponential plasma density ramp with higher order value of axial electron temperature has been done. Beam width parameter is derived by using paraxial ray approximation and then solved numerically. It is seen that self-focusing of chirped pulse laser is intensely affected by the higher order values of axial electron temperature. Further, influence of exponential plasma density ramp is studied and it is concluded that self-focusing of laser enhances and occurs earlier. On the other hand defocusing of beam reduces to the great extent. It is noticed that the laser spot size reduces significantly under joint influence of the density ramp and the axial electron temperature. Present analysis may be useful for the analysis of quantum dots, the laser induced fusion and etc.

scholarly journals Design and Analysis of High Speed Low Power Hybrid Adder Using Transmission Gates

2016 ◽  
Vol 5 (03) ◽  
pp. 07-12
Author(s):  
Prof. Amruta Bijwar
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Arithmetic Operation ◽  
Vlsi Design ◽  
Full Adder ◽  
Basic Component ◽  
Xnor Gate ◽  
Transmission Gates ◽  
Design Systems ◽  
Complex Circuits

Addition is the vital arithmetic operation and it acts as a base for many arithmetic operations such as multipliers, dividers, etc. A full adder acts as a basic component in complex circuits. Full adder is the essential segment in many applications such as DSP, Microcontroller, Microprocessor, etc. There exists an inevitable swap between speed and power indulgence in VLSI design systems. A new modified hybrid 1-bit full adder using TG is presented. Here, the circuit is replaced with a simple XNOR gate, which increases the speed. Due to this, transistor count gets reduced results in better optimization of area. The analysis has been carried out also for 2, 4, 8 and 16 bit and it is compared with the various techniques. The result shows a significant improvement in speed, area, power dissipation and transistor counts.

The structure of Estonian personal values: a lexical approach

2002 ◽  
Vol 16 (3) ◽  
pp. 221-235 ◽  
Author(s):  
Toivo Aavik ◽  
Jüri Allik
Keyword(s):  
Principal Component Analysis ◽  
Personal Values ◽  
General Structure ◽  
Principal Component ◽  
Higher Order ◽  
The Self ◽  
The Other ◽  
Two Dimensional ◽  
Lexical Approach ◽  
Estonian Language

The main purpose of this paper is to investigate the variety of value describing words and interrelation of value categories in the Estonian language. To accomplish this aim, a psycholexical approach was adopted, during which a set of 560 value‐related words was selected from the Estonian Orthological Dictionary and the results were compared with the Schwartz Values Survey (SVS). When principal‐component analysis was applied on the self‐ratings of a reduced list of 78 value‐related words, six factors emerged and were labelled as benevolence, self‐enhancement, broadmindedness, hedonism, conservatism, and self‐realization. However, all these themes are interrelated and load on a singular secondary dimension. The constructs measured by SVS and the value categories in Estonian were only partially interchangeable; moderate correlations imply an imperfect correspondence: each theme was related to many categories on the other questionnaire. However, a significant general structure refers to the same two‐dimensional level of higher‐order values described by Schwartz in 1992. Copyright © 2002 John Wiley & Sons, Ltd.

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