Simulation Analysis of Circuit and Designing of PCB Layout of a CMOS based NOR Logic Gate using Open-Source Software eSim

There are various basic gates like NAND, NOR gates which are extensively used in the designing of the more complex circuits with use higher number of transistors such as MUXs, ADCs and any other circuits. In this paper, we have carried out the modelling of NOR gate at 130 nm technology, yet maintaining comparable performance than conventional CMOS NOR gate logic structure. The modelling includes schematics design and PCB layout design run of the above gates. Also, the simulation results of the gates are obtained at the same node with start time, step time, stop time, rise time, fall time and delay and power dissipation. In this all process have been carried out of a CMOS based NOR Logic Gate using Open-Source Software eSim. Keywords: Simulation, PCB, NOR, CMOS, eSim

Automated Design and Implementation of a NOR Gate in Pseudomonas Putida

ABSTRACT Boolean NOR gates have been widely implemented in Escherichia coli as transcriptional regulatory devices for building complex genetic circuits. Yet, their portability to other bacterial hosts/chassis is generally hampered by frequent changes in the parameters of the INPUT/OUTPUT response functions brought about by new genetic and biochemical contexts. Here, we have used the circuit design tool CELLO for assembling a NOR gate in the soil bacterium and metabolic engineering platform Pseudomonas putida with components tailored for E. coli. To this end, we capitalized on the functional parameters of 20 genetic inverters for each host and the resulting compatibility between NOT pairs. Moreover, we added to the gate library 3 inducible promoters that are specific to P. putida, thus expanding cross-platform assembly options. While the number of potential connectable inverters decreased drastically when moving the library from E. coli to P. putida, the CELLO software was still able to find an effective NOR gate in the new chassis. Automated generation of the corresponding DNA sequence and in vivo experimental verification accredited that some genetic modules initially optimized for E. coli can indeed be reused to deliver NOR logic in P. putida as well. Furthermore, the results highlight the value of creating host-specific collections of well-characterized regulatory inverters for quick assembly of genetic circuits to meet complex specifications.

Design of Universal Logic Gates Using Homo and Hetero-Junction Double Gate TFETs with Pseudo-Derived Logic

This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 103 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 103 times and less propagation delay than that of hetero-junction NOR logic circuit

Simulation study of memristor aided logic (MAGIC) based on CMOS NOR gate

Memristor is a non-volatile new technology memory where the data stored as a resistance which the performance is influenced by the stateful logic design. Therefore, this study is an attempt to investigate the performance of the MAGIC NOR Gate stateful logic design using LTSPICE and targeted to 2 bits memory application. The objective is to investigate the performance of memristor based stateful logic logic design and schematics for memory application. Furthermore, the study been carried out by implementing the MAGIC NOR gate stateful logic schematic, then simulate the design in order to see the effects of performance including the electrical parameters compared to the others. Evidently, the improvement of MAGIC NOR gate contributes in reducing the number of NOR gate and CMOS count. Besides, the MAGIC NOR gates takes parallel inputs topology and eliminate the threshold voltage compared to IMPLY logic. Nevertheless, larger numbers of memristor required to stable the output consistency in MAGIC NOR gate schematic.