FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design

In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, and the circuit of AND gate and OR gate composed of memristors is built by using this model. Combined with the original NOT gate in FPGA, the NAND gate, NOR gate, XOR gate and the XNOR gate are further realized, and then the adder design is completed. Compared with the traditional gate circuit, this model has obvious advantages in size and non-volatility. At the same time, the establishment of this model will add new research methods and tools for memristor simulation research.

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Logic Circuit Design with DGMOS Devices

Planar Double-Gate Transistor ◽

10.1007/978-1-4020-9341-8_7 ◽

2009 ◽

pp. 137-165

Author(s):

Ian O'Connor ◽

Ilham Hassoune ◽

Xi Yang ◽

David Navarro

Keyword(s):

Circuit Design ◽

Logic Circuit

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Three-dimensional lattice logic circuits, Part I: Fundamentals

Facta universitatis - series Electronics and Energetics ◽

10.2298/fuee0501001a ◽

2005 ◽

Vol 18 (1) ◽

pp. 1-13 ◽

Cited By ~ 4

Author(s):

Anas Al-Rabadi

Keyword(s):

Circuit Design ◽

Fault Localization ◽

Three Dimensional ◽

Logic Circuits ◽

Logic Circuit ◽

Device Performance ◽

Important Class ◽

Future Directions ◽

Dimensional Lattice ◽

Current Technology

Fundamentals of regular three-dimensional (3D) lattice circuits are introduced. Lattice circuits represent an important class of regular circuits that allow for local interconnections, predictable timing, fault localization, and self-repair. In addition, three-dimensional lattice circuits can be potentially well suited for future 3D technologies, such as nanotechnologies, where the intrinsic physical delay of the irregular and lengthy interconnections limits the device performance. Although the current technology does not offer a menu for the immediate physical implementation of the proposed three-dimensional circuits, this paper deals with three-dimensional logic circuit design from a fundamental and foundational level for a rather new possible future directions in designing digital logic circuits.

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Contents Development of PBL-based Integrant Design Course for Creative Design Capability -Focusing on Logic Circuit Design Textbook-

Journal of Digital Contents Society ◽

10.9728/dcs.2012.13.3.413 ◽

2012 ◽

Vol 13 (3) ◽

pp. 413-420 ◽

Cited By ~ 1

Author(s):

Jae-Min Lee

Keyword(s):

Circuit Design ◽

Logic Circuit ◽

Creative Design

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Nanobridge gate-all-around phototransistors for electro-optical OR gate circuit and frequency doubler applications

Applied Physics Letters ◽

10.1063/1.4862328 ◽

2014 ◽

Vol 104 (2) ◽

pp. 022110 ◽

Cited By ~ 4

Author(s):

Jin Yong Oh ◽

M. Saif Islam

Keyword(s):

Frequency Doubler ◽

Gate Circuit ◽

Or Gate

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The Logic Circuit Design of Fire Alarm System Device by DNA Strand Displacement

Communications in Computer and Information Science - Bio-inspired Computing: Theories and Applications ◽

10.1007/978-981-10-7179-9_28 ◽

2017 ◽

pp. 369-379

Author(s):

Yanfeng Wang ◽

Jixiang Li ◽

Chun Huang ◽

Junwei Sun

Keyword(s):

Circuit Design ◽

Logic Circuit ◽

Alarm System ◽

Strand Displacement ◽

Fire Alarm ◽

Dna Strand Displacement ◽

Fire Alarm System ◽

Dna Strand

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Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

Journal of Circuits System and Computers ◽

10.1142/s0218126620501364 ◽

2019 ◽

Vol 29 (09) ◽

pp. 2050136

Author(s):

Yuuki Tanaka ◽

Yuuki Suzuki ◽

Shugang Wei

Keyword(s):

Field Programmable Gate Array ◽

High Speed ◽

Number System ◽

Logic Circuit ◽

Fpga Implementation ◽

Number Representation ◽

Representation System ◽

Representation Systems ◽

Field Programmable ◽

Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

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Signal Processing Circuit Design Based on SOPC Technology for the Electric Field Type Time Grating Sensors

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.635-637.755 ◽

2014 ◽

Vol 635-637 ◽

pp. 755-759

Author(s):

Fang Yan Zheng ◽

Zi Ran Chen ◽

Zhi Cheng Yu

Keyword(s):

Signal Processing ◽

Electric Field ◽

Circuit Design ◽

Linear Time ◽

Measuring Error ◽

Field Type ◽

Field Programmable ◽

System On Programmable Chip ◽

Processing Circuit ◽

Signal Field

Signal processing circuits are proposed for the electric field type time grating sensors. The proposed design scheme integrates sampling function and processing function into a signal field programmable gate array (FPGA) based on system on programmable chip (SOPC) technology. Employing NiosII technology and adding self-defined instructions improve data processing speed for time grating sensors. The proposed signal processing circuits are simple and stabile. The proposed signal processing circuits are applied to electric field type linear time grating sensors, the experiments results that the peak-to peak measuring error is 0.3um within 200mm without any corrections.

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