Degradation mechanisms analysis for SiC power MOSFETs under repetitive power cycling stress

In this work, investigation on the degradation behavior of the 1.2-kV/52-A silicon carbide (SiC) power MOSFETs subjected to repetitive slow power cycling stress have been performed. Electric characteristics have been characterized periodically over the stress and the respective degradation mechanisms also have been analysed. A comprehensive degradation analysis is further conducted after the aging test by virtue of the X-ray inspection system, Scanning Acoustic Microscope (SAM), Scanning Electron Microscope (SEM) and emission microscope (EMMI), etc. Experimental results reveal that both the degradation of gate oxide on chip-level and the degradation of the bond wire and solder layer on package-level have emerged over the cyclic stress. Specifically, growths of threshold voltage (Vth) and gate leakage current (Igss) are thought to be relevant with the degradation of gate oxide by SiC/SiO2 interface states trapping/de-trapping electron on chip-level, while the appearances of the fatigue of bond wire and the delamination of solder layer imply the degradation on package-level. This work may provide some practical guidelines for the assessments towards the reliability of SiC power MOSFETs in power conversion system.

A Bond-Wire Drift Offset Minimized Capacitance-to-Digital Interface for MEMS Accelerometer with Gain-Enhanced VCO-Based Quantization and Nested Digital Chopping Feedback Loops

This paper presents an output offset minimized capacitance-to-digital interface for a MEMS accelerometer. With a gain-enhanced voltage-controlled oscillator (VCO)-based quantization loop, the interface is able to output a digital signal with improved dynamic range. For optimizing the output offset caused by nonideal factors (e.g., the bond-wire drift), a nested digital chopping feedback loop is embedded in the VCO-based quantization loop. It enables the interface to minimize the output offset without digital filtering and digital-to-analog conversion. The proposed architecture is well suited for dynamic range and offset improvements with low cost. Fabricated with a 0.18 μm Global Foundry (GF) CMOS process, the interface offers a 78 dB dynamic range with 0.4% nonlinearity from a single 2 V supply. With the input referred offset up to 1.3 pF, the offset cancellation loop keeps the DC output offset within 40 mV. The power dissipation is 6.5 mW with a bandwidth of 4 kHz.

An Anti-Interference Online Monitoring Method for IGBT Bond Wire Aging

Due to the constant changes of the environment and load, the insulated-gate bipolar transistor (IGBT) module is subjected to a large amount of junction temperature (Tj) fluctuations, which often leads to damage to the bond wires. The monitoring parameters of IGBTs are often coupled with Tj, which increases the difficulty of monitoring IGBTs’ health status online. In this paper, based on the collector current (Ic) and collector-emitter on-state voltage (Vce_on) online monitoring circuit, an online monitoring method of IGBT bond wire aging against interference is proposed. First, the bond wire aging model is established, and the Vce_on is selected as the monitoring parameter. Secondly, taking a three-phase inverter circuit as an example, the Vce_on and Ic waveforms of the IGBT module are monitored in real time, and the process of online monitoring is introduced accordingly. Finally, the experimental results indicate that the method proposed in this paper can accurately identify the aging state of IGBT bond wires under different conditions.

Effect of load sequence interaction on bond-wire lifetime due to power cycling

Experimental investigations on the effects of load sequence on degradations of bond-wire contacts of Insulated Gate Bipolar Transistors power modules are reported in this paper. Both the junction temperature swing ($$\Delta T_{j}$$ Δ T j ) and the heating duration ($$t_{ON}$$ t ON ) are investigated. First, power cycling tests with single conditions (in $$\Delta T_{j}$$ Δ T j and $$t_{ON}$$ t ON ), are performed in order to serve as test references. Then, combined power cycling tests with two-level stress conditions have been done sequentially. These tests are carried-out in the two sequences: low stress/high stress (LH) and high stress/low stress (HL) for both $$\Delta T_{j}$$ Δ T j and $$t_{ON}$$ t ON . The tests conducted show that a sequencing in $$\Delta T_{j}$$ Δ T j regardless of the direction “high-low” or “low–high” leads to an acceleration of degradations and so, to shorter lifetimes. This is more pronounced when the difference between the stress levels is large. With regard to the heating duration ($$t_{ON}$$ t ON ), the effect seems insignificant. However, it is necessary to confirm the effect of this last parameter by additional tests.