Degradation mechanisms analysis for SiC power MOSFETs under repetitive power cycling stress

In this work, investigation on the degradation behavior of the 1.2-kV/52-A silicon carbide (SiC) power MOSFETs subjected to repetitive slow power cycling stress have been performed. Electric characteristics have been characterized periodically over the stress and the respective degradation mechanisms also have been analysed. A comprehensive degradation analysis is further conducted after the aging test by virtue of the X-ray inspection system, Scanning Acoustic Microscope (SAM), Scanning Electron Microscope (SEM) and emission microscope (EMMI), etc. Experimental results reveal that both the degradation of gate oxide on chip-level and the degradation of the bond wire and solder layer on package-level have emerged over the cyclic stress. Specifically, growths of threshold voltage (Vth) and gate leakage current (Igss) are thought to be relevant with the degradation of gate oxide by SiC/SiO2 interface states trapping/de-trapping electron on chip-level, while the appearances of the fatigue of bond wire and the delamination of solder layer imply the degradation on package-level. This work may provide some practical guidelines for the assessments towards the reliability of SiC power MOSFETs in power conversion system.