A High Precision, Wide Operating Range Charge Pump Circuit in a Phase Locked Loop for a CMOS Image Sensor

2021 ◽  
Vol 19 (8) ◽  
pp. 59-65
Author(s):  
Jimin Cheon
Keyword(s):  
High Precision ◽  
Charge Pump ◽  
Cmos Image Sensor ◽  
Phase Locked Loop ◽  
Image Sensor ◽  
Operating Range ◽  
Charge Pump Circuit ◽  
Wide Operating

scholarly journals A synchronous driving approach based on adaptive delay phase-locked loop for stitching CMOS image sensor

2020 ◽  
Vol 17 (3) ◽  
pp. 20190642-20190642
Author(s):  
Zhongjie Guo ◽  
Ningmei Yu ◽  
Longsheng Wu
Keyword(s):  
Cmos Image Sensor ◽  
Phase Locked Loop ◽  
Image Sensor

A CMOS Image Sensor with a Novel Passive Pixel Array and High Precision Current Amplifier for a Compact Digital X-ray Detector

2020 ◽  
Vol 10 (11) ◽  
pp. 2745-2753
Author(s):  
Jimin Cheon ◽  
Dongmyung Lee ◽  
Hojong Choi
Keyword(s):  
High Precision ◽  
Dynamic Range ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Total Power ◽  
Cmos Process ◽  
Current Amplifier ◽  
X Ray ◽  
Total Power Consumption ◽  
Pixel Array

An active pixel sensor (APS) in a digital X-ray detector is the dominant circuitry for a CMOS image sensor (CIS) despite its lower fill factor (FF) compared to that of a passive pixel sensor (PPS). Although the PPS provides higher FF, its overall signal-to-noise ratio (SNR) is lower than that of the APS. The required high resolution and small focal plane can be achieved by reducing the number of transistors and contacts per pixel. We proposed a novel passive pixel array and a high precision current amplifier to improve the dynamic range (DR) without minimizing the sensitivity for diagnostic compact digital X-ray detector applications. The PPS can be an alternative to improve the FF. However, size reduction of the feedback capacitor causes degradation of SNR performance. This paper proposes a novel PPS based on readout and amplification circuits with a high precision current amplifier to minimize performance degradation. The expected result was attained with a 0.35-μm CMOS process parameter with power supply voltage of 3.3 V. The proposed PPS has a saturation signal of 1.5 V, dynamic range of 63.5 dB, and total power consumption of 13.47 mW. Therefore, the proposed PPS readout circuit improves the dynamic range without sacrificing the sensitivity.

A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP

2005 ◽  
Vol 14 (05) ◽  
pp. 997-1006 ◽  
Author(s):  
ROBERT C. CHANG ◽  
LUNG-CHIH KUO ◽  
HOU-MING CHEN
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Low Power Cmos ◽  
Charge Pump Circuit ◽  
Frequency Detector

A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can be generated with a single supply voltage of 1.5 V. The power dissipation of the circuit is 9.17 mW.

A low spur CMOS phase-locked loop with wide tuning range for CMOS Image Sensor

2013 ◽  
Author(s):  
Zhiqing Chen ◽  
Qi Zhang ◽  
Ning Wang ◽  
Dunshan Yuan ◽  
Guohong Li ◽  
...  
Keyword(s):  
Tuning Range ◽  
Cmos Image Sensor ◽  
Phase Locked Loop ◽  
Image Sensor ◽  
Wide Tuning Range

Development of Wafer Level Chip Size Packaging Process and its Application to the CMOS Image Sensor Module for Medical Device

2017 ◽  
Vol 137 (2) ◽  
pp. 48-58
Author(s):  
Noriyuki Fujimori ◽  
Takatoshi Igarashi ◽  
Takahiro Shimohata ◽  
Takuro Suyama ◽  
Kazuhiro Yoshida ◽  
...  
Keyword(s):  
Medical Device ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Wafer Level ◽  
Packaging Process ◽  
Sensor Module ◽  
Chip Size

An Over 120dB Dynamic Range Linear Response Single Exposure CMOS Image Sensor with Two-stage Lateral Overflow Integration Trench Capacitors

2020 ◽  
Vol 2020 (7) ◽  
pp. 143-1-143-6 ◽  
Author(s):  
Yasuyuki Fujihara ◽  
Maasa Murata ◽  
Shota Nakayama ◽  
Rihito Kuroda ◽  
Shigetoshi Sugawa
Keyword(s):  
Linear Response ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Signal To Noise ◽  
Single Exposure ◽  
Two Stage ◽  
Noise Ratio ◽  
Maximum Signal

This paper presents a prototype linear response single exposure CMOS image sensor with two-stage lateral overflow integration trench capacitors (LOFITreCs) exhibiting over 120dB dynamic range with 11.4Me- full well capacity (FWC) and maximum signal-to-noise ratio (SNR) of 70dB. The measured SNR at all switching points were over 35dB thanks to the proposed two-stage LOFITreCs.

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