silver sintering
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2021 ◽  
Author(s):  
Steffen Hadeler ◽  
Henning Seefisch ◽  
Rico Ottermann ◽  
Yangyang Long ◽  
Folke Dencker ◽  
...  

2021 ◽  
Author(s):  
Christian Hofmann ◽  
Mario Baum ◽  
Maulik Satwara ◽  
Martin Kroll ◽  
Sushant Panhale ◽  
...  

Author(s):  
Chin-Hao Tsai ◽  
Wei-Chen Huang ◽  
Ly May Chew ◽  
Wolfgang Schmitt ◽  
Jiahui Li ◽  
...  

2021 ◽  
pp. 114206
Author(s):  
N. Botter ◽  
R. Khazaka ◽  
Y. Avenas ◽  
J.M. Missiaen ◽  
D. Bouvard ◽  
...  

2021 ◽  
Vol 11 (15) ◽  
pp. 7012
Author(s):  
Michele Calabretta ◽  
Alessandro Sitta ◽  
Salvatore Massimo Oliveri ◽  
Gaetano Sequenzia

The increasing demand in automotive markets is leading the semiconductor industries to develop high-performance and highly reliable power devices. Silicon carbide MOSFET chips are replacing silicon-based solutions through their improved electric and thermal capabilities. In order to support the development of these novel semiconductors, packaging technologies are evolving to provide enough reliable products. Silver sintering is one of the most promising technologies for die attach. Due to their superior reliability properties with respect to conventional soft solder compounds, dedicated reliability flow and physical analyses should be designed and employed for sintering process optimization and durability assessment. This paper proposes an experimental methodology to optimize the pressure value applied during the silver sintering manufacturing of a silicon carbide power MOSFET molded package. The evaluation of the best pressure value is based on scanning electron microscopy performed after a liquid-to-liquid thermal shock reliability test. Furthermore, the sintering layer degradation is monitored during durability stress by scanning the acoustic microscopy and electric measurement of a temperature sensitive electric parameter. Moreover, mechanical elastoplastic behavior is characterized by uniaxial tensile test for a bulk sample and finite element analysis is developed to predict the mechanical behavior as a function of void fraction inside sintering layer.


2021 ◽  
Vol 2021 (HiTEC) ◽  
pp. 000018-000024
Author(s):  
Holger Kappert ◽  
Sebastian Braun ◽  
Norbert Kordas ◽  
Andre Kosfeld ◽  
Alexander Utz ◽  
...  

Abstract Sensors are key elements for capturing environmental properties and are increasingly important in the industry for the intelligent control of industrial processes. While in many everyday objects highly integrated sensor systems are already state of the art, the situation in an industrial environment is clearly different. Frequently the use of sensor systems is impossible, because the extreme ambient conditions of industrial processes like high operating temperatures or strong mechanical load do not allow a reliable operation of sensitive electronic components. Fraunhofer is running the Lighthouse Project ‘eHarsh’ to overcome this hurdle. In the course of the project an integrated sensor readout electronic has been realized based on a set of three chips. A dedicated sensor frontend provides the analog sensor interface for resistive sensors typically arranged in a Wheatstone configuration. Furthermore, the chipset includes a 32-bit microcontroller for signal conditioning and sensor control. Finally, it comprises an interface chip including a bus transceiver and voltage regulators. The chipset has been realized in a high temperature 0.35 micron SOI-CMOS technology focusing operating temperatures up to 300 °C. The chipset is assembled on a multilayer ceramic LTCC-board using flip chip technology. The ceramic board consists of 4 layers with a total thickness of approx. 0.9 mm. The internal wiring is based on silver paste while external contacts were alternatively manufactured in silver (sintering/soldering) or in gold-alloys (wire bonding). As interconnection technology, silver sintering has been applied. It has already been shown that a significant increase in lifetime can be reached by using silver sintering for die attach applications. Using silver sintering for flip chip technology is a new and challenging approach. By adjusting the process parameter geared to the chipset design and the design of the ceramic board high quality flip chip interconnects can be generated.


2020 ◽  
Vol 114 ◽  
pp. 113900
Author(s):  
F. Arabi ◽  
T. Youssef ◽  
M. Coudert ◽  
G. Coquery ◽  
N. Alayli ◽  
...  
Keyword(s):  

2020 ◽  
Vol 114 ◽  
pp. 113890
Author(s):  
Chang-Chun Lee ◽  
Kuo-Shu Kuo ◽  
Chi-Wei Wang ◽  
Jing-Yao Chang ◽  
Wei-Kuo Han ◽  
...  

2020 ◽  
Vol 114 ◽  
pp. 113891
Author(s):  
A. Tablati ◽  
N. Alayli ◽  
T. Youssef ◽  
O. Belnoue ◽  
L. Theolier ◽  
...  

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