scholarly journals MINIATURE IMPROVED CARRY SELECT ADDER WITH ADVANCE FEATURES AND POWER REQUIREMENTS

2014 ◽  
pp. 99-103
Author(s):  
D. KRISHNA NAIK ◽  
DR V. VIJAYALAKSHMI
Keyword(s):  
Power Consumption ◽  
Data Processing ◽  
Arithmetic Functions ◽  
Square Root ◽  
Carry Select Adder ◽  
Overall Efficiency ◽  
Better Than

In most of the data processing processors to perform arithmetic functions Carry Select Adder (CSLA) is used as this is one of the fastest adders. In order to increase the overall efficiency of the processor we can reduce the area and power consumption of the CSLA of processors. Based on this premise we can modify the regular SQRT CSLA architecture as 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

scholarly journals Design of Carry Select Adder using BEC and Common Boolean Logic

2022 ◽  
pp. 5-9
Author(s):  
Syed Mustafaa M ◽  
◽  
Sathish M ◽  
Nivedha S ◽  
Magribatul Noora A K ◽  
...  
Keyword(s):  
Power Consumption ◽  
Dynamic Method ◽  
Boolean Logic ◽  
Square Root ◽  
Large Area ◽  
Carry Select Adder ◽  
Great Scope

Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and power consumption in a great way we proposed a design using binary to excess 1 converter (BEC). This paper proposes an dynamic method which replaces a BEC using Common Boolean Logic.

scholarly journals Simple and rapid gas sensing using a single-walled carbon nanotube field-effect transistor-based logic inverter

2021 ◽  
Author(s):  
Salomé Forel ◽  
Leandro Sacco ◽  
Alice Castan ◽  
Ileana Florea ◽  
Costel Sorin Cojocaru
Keyword(s):  
Carbon Nanotube ◽  
Power Consumption ◽  
Data Processing ◽  
Gas Sensor ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Gas Sensing ◽  
Single Walled Carbon Nanotube ◽  
Effect Transistor ◽  
System Miniaturization

We design a gas sensor by combining two SWCNT-FET devices in an inverter configuration enabling a better system miniaturization together with a reduction of power consumption and ease of data processing.

Second Paper: Deep Drawing and Free Forming Using a Water Hammer Technique

1964 ◽  
Vol 179 (1) ◽  
pp. 222-233 ◽  
Author(s):  
A. P. Vafiadakis ◽  
W. Johnson ◽  
I. S. Donaldson
Keyword(s):  
Deep Drawing ◽  
Time History ◽  
Water Hammer ◽  
High Rate ◽  
Pressure Time ◽  
Order Of Magnitude ◽  
History Of ◽  
Overall Efficiency ◽  
Initial Movement ◽  
Better Than

Earlier work on a water-hammer technique for high-rate forming of sheet metal has been extended to include work on deep drawing using lead plugs. A study of the pressure-time history of a deforming blank during its initial movement is reported. An assessment of the overall efficiency of the process has been made and is found to be about 50 per cent; this is an order of magnitude better than that found with comparable electro-hydraulic and explosive methods.

An Improved Wavelet Threshold De-Noising Data Processing Method Research in Deformation Monitoring

2011 ◽  
Vol 90-93 ◽  
pp. 2858-2863
Author(s):  
Wei Li ◽  
Xu Wang
Keyword(s):  
Data Processing ◽  
Deformation Monitoring ◽  
Processing Method ◽  
Threshold Function ◽  
Wavelet Coefficients ◽  
New Approach ◽  
Data Processing Method ◽  
Soft Threshold ◽  
Fixed Bias ◽  
Better Than

Due to the soft and hard threshold function exist shortcomings. This will reduce the performance in wavelet de-noising. in order to solve this problem，This article proposes Modulus square approach. the new approach avoids the discontinuity of the hard threshold function and also decreases the fixed bias between the estimated wavelet coefficients and the wavelet coefficients of the soft-threshold method．Simulation results show that SNR and MSE are better than simply using soft and hard threshold，having good de-noising effect in Deformation Monitoring.

scholarly journals Image Retrieval Using the Intensity Variation Descriptor

2020 ◽  
Vol 2020 ◽  
pp. 1-12 ◽  
Author(s):  
Zhao Wei ◽  
Guang-Hai Liu
Keyword(s):  
Image Retrieval ◽  
Information Extraction ◽  
Lateral Inhibition ◽  
Intensity Variation ◽  
Spatial Layout ◽  
Inhibition Mechanism ◽  
Square Root ◽  
Optimal Direction ◽  
Selective Mechanism ◽  
Better Than

Variations between image pixel characteristics contain a wealth of information. Extraction of such cues can be used to describe image content. In this paper, we propose a novel descriptor, called the intensity variation descriptor (IVD), to represent variations in colour, edges, and intensity and apply it to image retrieval. The highlights of the proposed method are as follows. (1) The IVD combines the advantages of the HSV and RGB colour spaces. (2) It can simulate the lateral inhibition mechanism and orientation-selective mechanism to determine an optimal direction and spatial layout. (3) An extended weighted L1 distance metric is proposed to calculate the similarity of images. It does not require complex operations such as square or square root and leads to good performance. Comparative experiments on two Corel datasets containing 15,000 images show that the proposed method performs better than the SoC-GMM, CPV-THF, and STH methods and provides good matching of texture, colour, and shape.

scholarly journals FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
V. Kokilavani ◽  
K. Preethi ◽  
P. Balasubramanian
Keyword(s):  
High Speed ◽  
Boolean Logic ◽  
The Other ◽  
Square Root ◽  
Verilog Hdl ◽  
Other Hand ◽  
Carry Select Adder

Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work, two new hybrid carry select adders are proposed involving the carry select and section-carry based carry lookahead subadders with/without binary to excess 1 converters. Seven different carry select adders were implemented in Verilog HDL and their performances were analyzed under two scenarios, dual-operand addition and multioperand addition, where individual operands are of sizes 32 and 64-bits. In the case of dual-operand additions, the hybrid carry select adder comprising the proposed carry select and section-carry based carry lookahead configurations is the fastest. With respect to multioperand additions, the hybrid carry select adder containing the carry select and conventional carry lookahead or section-carry based carry lookahead structures produce similar optimized performance.

An Improved Method on Telemetry Data Processing

2014 ◽  
Vol 610 ◽  
pp. 454-456
Author(s):  
Chun Hui He ◽  
Shi Bin Su ◽  
Kai Da Huang
Keyword(s):  
Data Processing ◽  
Qualitative Analysis ◽  
Conventional Method ◽  
Improved Method ◽  
Telemetry Data ◽  
Simulation Results ◽  
Better Than

In reference to telemetry data processing, an improved method is presented, which makes use of telemetry data that the conventional method abandons. Qualitative analysis is made to show the advantage of the improved method. Simulation results indicate that the improved method can obtain 1~3dB gain, better than the conventional method.

scholarly journals Comprehensive Analysis of SRAM Cell Architectures With 18nm FinFET for Low Power Applications

2021 ◽  
Author(s):  
T. Santosh Kumar ◽  
Suman Lata Tripathi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Reduction Technique ◽  
Leakage Currents ◽  
Leakage Reduction ◽  
Sram Cell ◽  
Supply Voltage Scaling ◽  
Better Than

Abstract The SRAM cells are used in many applications where power consumption will be the main constraint. The Conventional 6T SRAM cell has reduced stability and more power consumption when technology is scaled resulting in supply voltage scaling, so other alternative SRAM cells from 7T to 12T have been proposed which can address these problems. Here a low power 7T SRAM cell is suggested which has low power consumption and condensed leakage currents and power dissipation. The projected design has a leakage power of 5.31nW and leakage current of 7.58nA which is 84.9% less than the 7T SRAM cell without using the proposed leakage reduction technique and it is 22.4% better than 6T SRAM and 22.1% better than 8T SRAM cell when both use the same leakage reduction technique. The cell area of the 7T SRAM cell is 1.25µM2, 6T SRAM is 1.079µM2 and that of 8T SRAM is 1.28µM2all the results are simulated in cadence virtuoso using 18nm technology.

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