Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits

Reversible Computation - Lecture Notes in Computer Science ◽

10.1007/978-3-319-20860-2_17 ◽

2015 ◽

pp. 267-272 ◽

Cited By ~ 1

Author(s):

Samer Houri ◽

Gerard Billiot ◽

Marc Belleville ◽

Alexandre Valentian ◽

Herve Fanet

Keyword(s):

Logic Circuits ◽

Clock Generator ◽

Adiabatic Logic

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Four-phase power clock generator for adiabatic logic circuits

Electronics Letters ◽

10.1049/el:20020523 ◽

2002 ◽

Vol 38 (14) ◽

pp. 689 ◽

Cited By ~ 18

Author(s):

A. Bargagli-Stoffi ◽

G. Iannaccone ◽

S. Di Pascoli ◽

E. Amirante ◽

D. Schmitt-Landsiedel

Keyword(s):

Logic Circuits ◽

Clock Generator ◽

Adiabatic Logic

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Near-Threshold Flip-Flops Using Clocked Adiabatic Logic in Nanometer CMOS Processes

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.460-461.837 ◽

2011 ◽

Vol 460-461 ◽

pp. 837-842 ◽

Cited By ~ 2

Author(s):

Hai Yan Ni ◽

Jian Ping Hu

Keyword(s):

Single Phase ◽

Energy Savings ◽

Logic Circuits ◽

Sequential Circuits ◽

Clock Generator ◽

Nanometer Cmos ◽

Wide Range ◽

Adiabatic Logic ◽

Auxiliary Signal ◽

Near Threshold

This paper presents adiabatic flip-flops operating on near-threshold supply voltages. The near-threshold adiabatic flip-flops and sequential circuits are realized with improved CAL (Clocked Adiabatic Logic) circuits using a single-phase power clock. An auxiliary clock generator is used to obtain the non-overlap sinusoidal auxiliary signal pair. A near-threshold mode-10 counter is implemented. All circuits are simulated using Predictive Technology Model (PTM) 45nm process. The near-threshold adiabatic circuits attain large energy savings over a wide range of frequencies, as compared with conventional static CMOS logic circuits.

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TWO-PHASE SINUSOIDAL POWER-CLOCKED QUASI-ADIABATIC LOGIC CIRCUITS

Journal of Circuits System and Computers ◽

10.1142/s0218126610006098 ◽

2010 ◽

Vol 19 (02) ◽

pp. 335-347 ◽

Cited By ~ 15

Author(s):

V. S. KANCHANA BHAASKARAN ◽

J. P. RAINA

Keyword(s):

Low Frequency ◽

Cmos Technology ◽

Logic Circuits ◽

Wide Frequency Range ◽

Clock Generator ◽

Two Phase ◽

Sense Amplifier ◽

Adiabatic Logic ◽

And Performance ◽

Performance Validation

This paper presents the design and performance analysis of the dual-rail encoded and sense-amplifier structured 2N–2P, 2N–2N2P, IPGL and PFAL quasi-adiabatic circuits operated by two-phase sinusoidal power-clock sources. The energetics of these families are studied for varying power-clock voltages. The drivability characteristics are evaluated using capacitive loads. The performance validation is made through 8-bit and 16-bit adder circuits using an integrated power-clock generator. Optimal adiabatic gain values are achieved for 2N–2N2P and IPGL circuits across a wide frequency range. Energy recovery comparison between the four-phase ramp and two-phase sine power-clocks is made. The results demonstrate the efficiency of sinusoidal power clock at both the high and the low frequency ranges of operation. The circuits were designed using 180 nm CMOS technology.

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