scholarly journals The Ramped-step Voltage in Adiabatic Logic Circuits: Analysis of Parameters to Further Reduce Power Dissipation

2013 ◽  
Vol 5 (1) ◽  
pp. 114-117
Author(s):  
Nazrul Anuar Nayan ◽  
Yasuhiro Takahashi ◽  
Toshikazu Sekine
Keyword(s):  
Power Dissipation ◽  
Logic Circuits ◽  
Step Voltage ◽  
Adiabatic Logic

Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs

2014 ◽  
Vol 57 (4) ◽  
pp. 1-13 ◽  
Author(s):  
Kai Liao ◽  
XiaoXin Cui ◽  
Nan Liao ◽  
KaiSheng Ma ◽  
Di Wu ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Logic Circuits ◽  
Ultra Low Power ◽  
Adiabatic Logic ◽  
Low Power Dissipation ◽  
Pass Transistor

scholarly journals Design of Low Power Multiplexer and De-Multiplexer using Different Adiabatic Logics

2020 ◽  
Vol 9 (1) ◽  
pp. 465-473
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Digital Circuit ◽  
Logic Circuits ◽  
Digital Circuit Design ◽  
Adiabatic Logic ◽  
Low Power Dissipation ◽  
In Series ◽  
Main Factor

In this paper we proposed, design and evaluation of 16:1 Multiplexer and 1:16 Demultiplexer using different adiabatic logics. Power consumption is the main factor in VLSI digital circuit design. Here we have introduced a CMOS-logic based 16:1 Multiplexer and 1:16 De-multiplexer with a low power adiabatic logic. In which we concentrate on the characteristics of the CMOS and adiabatic logics such as 2N2P, 2N-2N2P and Dual sleep. Wherein both 2N2P and 2N2N2P use a cross-coupled transistor structure for adiabatic operation. Adiabatic logic circuits use reverse logic and the power dissipation will be less compared to the CMOS circuits as the inputs are given to the n-type functional tree in 2N2P and 2N2N2P. For dual sleep logic an additional circuit is connected in series with general CMOS circuit known as sleep circuit. we have concentrated on energy recovery and power dissipation, as all these technique results in the low power dissipation. Dualsleep is considered as the best of the all the other adiabatic and traditional logics

Power Dissipation Analysis of Adiabatic Circuits and Active Leakage Power Estimation in Nanometer CMOS Processes

2010 ◽  
Vol 121-122 ◽  
pp. 97-102 ◽  
Author(s):  
Wei Qiang Zhang ◽  
Li Su ◽  
Li Fang Ye ◽  
Jian Ping Hu
Keyword(s):  
Power Dissipation ◽  
Low Power Design ◽  
Logic Circuits ◽  
Leakage Power ◽  
Nanometer Cmos ◽  
Wide Range ◽  
Adiabatic Logic ◽  
Total Leakage ◽  
Pass Transistor ◽  
Simulation Results

The leakage dissipations of nano-circuits have become a critical concern. Estimating the leakage power of nano-circuits is very important in low-power design. This paper presents a new estimation technology for the active leakage dissipations of adiabatic logic circuits. Based on the power dissipation models of adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations with additional capacitances on load nodes of the adiabatic circuits using HSPICE simulations. Taken as an example, the estimation for dynamic and active leakage power dissipations of CPAL (Complementary Pass-transistor Adiabatic Logic) circuits is demonstrated using the proposed estimation technology. The simulation results show that the proposed estimation technology can accurately estimate the active leakage dissipations of CPAL circuits with an accepted error over a wide range of frequencies.

scholarly journals Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits

2015 ◽  
Vol 2015 ◽  
pp. 1-10
Author(s):  
Manoj Sharma ◽  
Arti Noor
Keyword(s):  
Circuit Design ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Average Power ◽  
Size Variation ◽  
Logic Circuits ◽  
Adiabatic Logic ◽  
Or Gate ◽  
Universal Gate ◽  
Circuit Family

Previously, authors have proposed CPLAG and MCPLAG circuits extracting benefits of CPL family implemented based upon semiadiabatic logic for low power VLSI circuit design along with gating concept. Also authors have communicated RCPLAG circuits adding another dimension of reconfigurability into CPLAG/MCPLAG circuits. Moving ahead, in this paper, authors have implemented/reconfigured RCPLAG universal Nand/And gate and universal Nor/Or gate for extracting behavior of dynamic positive edge triggered DFF. Authors have also implemented Adder/Subtractor circuit using different techniques. Authors have also reported modification in PFAL semiadiabatic circuit family to further reduce the power dissipation. Functionality of these is verified and found to be satisfactory. Further these are examined rigorously with voltage, Cload, temperature, and transistor size variation. Performance of these is examined with these variations with power dissipation, delays, rise, and fall times associated. From the analysis it is found that best operating condition for DFF based upon RCPLAG universal gate can be achieved at supply voltage lower than 3 V which can be used for different transistor size up to 36 μm. Average power dissipation is 0.2 μW at 1 V and 30 μW at 2 V at 100 ff Cload 25°C approximately. Average power dissipated by CPLAG Adder/Subtractot is 58 μW. Modified PFAL circuit reduces average power by 9% approximately.

Power-Clock Gating in Adiabatic Logic Circuits

2005 ◽  
pp. 638-646 ◽  
Author(s):  
Philip Teichmann ◽  
Jürgen Fischer ◽  
Stephan Henzler ◽  
Ettore Amirante ◽  
Doris Schmitt-Landsiedel
Keyword(s):  
Logic Circuits ◽  
Clock Gating ◽  
Adiabatic Logic

Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology

2019 ◽  
Vol 38 (9) ◽  
pp. 4338-4356
Author(s):  
Ajay Kumar Dadoria ◽  
Kavita Khare
Keyword(s):  
Low Power ◽  
Logic Circuits ◽  
Adiabatic Logic
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