Failure analysis of leakage current in plastic encapsulated packages

1990 ◽  
Vol 19 (11) ◽  
pp. 1319-1322 ◽  
Author(s):  
S. J. Hu ◽  
F. T. Cheang
Author(s):  
Y.E. Hong ◽  
M.T.T. We

Abstract As transistor dimension shrinks down below submicron to cater for higher speed and higher packing density, it is very important to characterize the shrinkage carefully to avoid unwanted parametric problems. Leakage current across short poly end-cap is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre wafer striping' functional failure problem. This paper presents the advanced failure analysis techniques and defect modeling used to narrow down and identify this new mechanism. Post process change by loosening the marginal poly end-cap criteria eliminated the problem completely.


Author(s):  
M. Versen ◽  
A. Schramm

Abstract A common failure signature in dynamic random access memories (DRAMs) is the single cell failure. The charge is lost and thereby the information stored in trench capacitors can be destroyed by high resistive leakage paths. The nature of the leakage path determines the properties of the failure such as temperature-, voltage- and timing-dependencies and its stability. In this study, high resistive leakage paths were investigated and delimited from classical shorts by estimating the order of magnitude of the leakage current and by comparison to a simple resistive leakage path. Such an investigation is the basis for a defect-based test approach that leads to multiparameter tests [1]. An introduction to the problem is given in the first section, while the second section deals with the characterization of the defects in two case studies. A short summary is given in the end.


1998 ◽  
Vol 512 ◽  
Author(s):  
M. Frischholz ◽  
K. Nordgren ◽  
K. Rottner ◽  
J. Seidel ◽  
A. Schöner ◽  
...  

ABSTRACTThe optical beam induced current (OBIC) technique allows a direct imaging of high voltage PN junctions at a microscopic level under reverse operating conditions by measuring the local variation of the photocurrent. In this paper we focus on the application of the UV-OBIC technique for failure analysis of 4H SiC high voltage P+N diodes.4H SiC P+N diodes with a 2-zone junction termination extension were used. The diodes were characterized in terms of reverse leakage current and breakdown voltage. Various devices were chosen for failure analysis on the base of early breakdown and/or excessive leakage current for OBIC measurements to study extrinsic failures. As a reference we selected diodes that blocked more than 2 kV with a leakage current density of typically less than 0.1 μA/cm2.OBIC measurements have been used to detect failures in devices that manifest themselves as peaks or “hot spots” in the photocurrent distribution. Early breakdown of diodes could be attributed to formation of hot spots in the periphery of the diodes. The appearance of a hot spot preceded any noticeable increase in reverse leakage current and is thus a very sensitive tool to identify defective diodes already at low voltage levels.The photocurrent generated by illumination of hot spots has been measured as a function of reverse bias voltage and the current multiplication factor has been determined.


2018 ◽  
Author(s):  
Chi Dang ◽  
Thanh Vo

Abstract An effective method is presented to locate certain failure sites on exposed junction of insulated-gate bipolar transistor (IGBT) devices. High emitter to collector leakage current, hereafter called ICESR, is an IGBT failure mode. The leakage current is typically related to the exposed P+/N+ junction on the die sidewall. Solder die attach residue bridging or silicon damage at this exposed P+/N+ junction are common causes of ICESR leakage. The die attach residue can be dislodged during decapsulation resulting in loss of failure information. A failure analysis flow will be described to precisely locate the ICESR leakage site without disturbing any possible die attach residue.


Author(s):  
Franco Stellari ◽  
Peilin Song ◽  
Alan J. Weger ◽  
Tian Xia

Abstract Light Emission due to Off-State Leakage Current (LEOSLC) is used in combination with the Picosecond Imaging Circuit Analysis (PICA) method to effectively diagnose and localize defects in a broken scan chain. As usual, the emission base method shows to be very effective in debugging the problem; the defect is successfully identified by the optical technique and confirmed by Physical Failure Analysis (PFA).


Author(s):  
Jaeho Won ◽  
Jundong Kim ◽  
Jina Kim ◽  
Jihye Shin ◽  
Jihoon Kim ◽  
...  

Abstract Leakage current from bit line to SNC (Storage Node Contact) is one of the most critical issues in DRAM operation. Such failure becomes more difficult to visualize as the device shrinks. In this study, bit line to SNC leakage fail was analyzed using nano-probing tool in 2xnm DRAM technology.


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