The Application of Novel Failure Analysis Techniques and Defect Modeling in Eliminating Short Poly End-Cap Problem in Submicron CMOS Devices

1996 ◽  
Author(s):  
Y.E. Hong ◽  
M.T.T. We
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Leakage Current ◽  
Packing Density ◽  
Process Change ◽  
Defect Modeling ◽  
Functional Failure ◽  
Analysis Techniques ◽  
Post Process ◽  
First Time

Abstract As transistor dimension shrinks down below submicron to cater for higher speed and higher packing density, it is very important to characterize the shrinkage carefully to avoid unwanted parametric problems. Leakage current across short poly end-cap is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre wafer striping' functional failure problem. This paper presents the advanced failure analysis techniques and defect modeling used to narrow down and identify this new mechanism. Post process change by loosening the marginal poly end-cap criteria eliminated the problem completely.

An Application of Breakthrough Failure Analysis Techniques in Eliminating Silicon Dislocation Problem in Sub-Micron CMOS Devices

1997 ◽  
Author(s):  
E. H. Yeoh ◽  
W. M. Mak ◽  
H. C. Lock ◽  
S. K. Sim ◽  
C. C. Ooi ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Packing Density ◽  
Failure Mechanisms ◽  
Potential Solution ◽  
Critical Dimensions ◽  
Functional Failure ◽  
Analysis Techniques ◽  
Root Cause ◽  
First Time

Abstract As device interconnect layers increase and transistor critical dimensions decrease below sub-micron to cater for higher speed and higher packing density, various new and subtle failure mechanisms have emerged and are becoming increasingly prevalent. Silicon dislocation is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre GFA wafer' functional failure problem. In this paper, several breakthrough failure analysis techniques used to narrow down and identify this new mechanism will be presented. Root cause determination and potential solution to this problem will also be discussed.

Unique Autoclave Stress Induced Failure Mechanism

2005 ◽  
Author(s):  
John Butchko ◽  
Bruce T. Gillette
Keyword(s):  
Corrosion Rate ◽  
Grain Boundary ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
Metal Corrosion ◽  
Corrosion Mechanism ◽  
Reliability Testing ◽  
Process Change ◽  
Transistor Reliability ◽  
Pass Through

Abstract Autoclave Stress failures were encountered at the 96 hour read during transistor reliability testing. A unique metal corrosion mechanism was found during the failure analysis, which was creating a contamination path to the drain source junction, resulting in high Idss and Igss leakage. The Al(Si) top metal was oxidizing along the grain boundaries at a faster rate than at the surface. There was subsurface blistering of the Al(Si), along with the grain boundary corrosion. This blistering was creating a contamination path from the package to the Si surface. Several variations in the metal stack were evaluated to better understand the cause of the failures and to provide a process solution. The prevention of intergranular metal corrosion and subsurface blistering during autoclave testing required a materials change from Al(Si) to Al(Si)(Cu). This change resulted in a reduced corrosion rate and consequently prevented Si contamination due to blistering. The process change resulted in a successful pass through the autoclave testing.

Techniques for Identification of Silver Migration in Plastic Encapsulated Devices Assembled with Molding Compound Containing Red Phosphorus Flame Retardant Material

2008 ◽  
Author(s):  
Ronald R. Hylton
Keyword(s):  
Failure Analysis ◽  
Flame Retardant ◽  
Failure Mechanism ◽  
Red Phosphorus ◽  
Molding Compound ◽  
Molding Compounds ◽  
Analysis Techniques

Abstract This paper describes the electrical signatures and failure analysis techniques used to identify plastic encapsulated devices that have failed due to silver migration. This migration, which produces resistive leakages between adjacent pins, has been associated with molding compounds that utilize red phosphorous as a flame retardant material. A description of the failure mechanism is also presented.

Physical Failure Analysis Techniques and Studies on Vertical Short Issue of 65nm Devices

2008 ◽  
Author(s):  
P.K. Tan ◽  
Z.H. Mai ◽  
S.L. Toh ◽  
E. Hendarto ◽  
Q. Deng ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
Semiconductor Devices ◽  
Nanoscale Devices ◽  
Nanometer Range ◽  
Analysis Techniques ◽  
Chemical Etch ◽  
Scaling Down

Abstract With the scaling down of semiconductor devices to nanometer range, physical failure analysis (PFA) has become more challenging. In this paper, a different method of performing PFA to identify a physical vertical short of intermetal layer in nanoscale devices is discussed. The proposed chemical etch and backside chemical etch PFA techniques have the advantages of sample preparation evenness and efficiency compared to conventional PFA. This technique also offers a better understanding of the failure mechanism and is easier to execute in identifying the vertical short issue.

Single Device Characterization by Nano-probing to Identify Failure Root Cause

2005 ◽  
Author(s):  
Chao-Chi Wu ◽  
Jon C. Lee ◽  
Jung-Hsiang Chuang ◽  
Tsung-Te Li
Keyword(s):  
Failure Analysis ◽  
Success Rate ◽  
Failure Mechanism ◽  
Fault Isolation ◽  
Device Characterization ◽  
Nano Technology ◽  
Analysis Techniques ◽  
Root Cause ◽  
Visual Defects ◽  
Lower Success Rate

Abstract In general failure analysis cases, a less invasive fault isolation approach can be utilized to resolve a visual root cause defect. In the case of nano technology, visual defects are not readily resolved, due to an increase in non-visible defects. The nonvisible defects result in a lower success rate since conventional FA methods/tools are not efficient in identifying the failure root cause. For the advanced nanometer process, this phenomenon is becoming more common; therefore the utilization of advanced techniques are required to get more evidence to resolve the failure mechanism. The use of nanoprobe technology enables advanced device characterization h order to obtain more clues to the possible failure mechanism before utilizing the traditional physical failure analysis techniques.

Residual Photoresist Identified as Cause for Frequency-Dependent Signal-to-Noise Failure After Autoclave Stress Testing

1999 ◽  
Author(s):  
Martin J. McVeigh
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Failure Mode ◽  
High Speed ◽  
Stress Testing ◽  
Signal To Noise ◽  
Analysis Techniques ◽  
Dependent Signal ◽  
Voltage Swing ◽  
Maximum Voltage

Abstract A case history is presented for the failure analysis of a 0.5u CMOS A/D converter in which high fallout occurred after autoclave stressing. The observed failure mode of degraded signal-to-noise distortion (SINAD) ratio (measured in dB) was found to affect devices within a specific bandwidth centered around 5MHz. From a circuit designer’s viewpoint, an explanation for this unique failure mode did not readily present itself. Yet, using straightforward failure analysis techniques, involving laser ablation of photoresist and selective etching of passivation, the specific failing circuit block was isolated. Crosssectional analysis, scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS) found evidence of residual photoresist at topography related voids in the nitride passivation layer. The photoresist reacts with moisture in the autoclave, resulting in increased capacitance at minimum-spaced top layer metal lines. This failure mechanism correlates with the observed maximum SINAD degradation around 5MHz: at this frequency the signals along the affected metal lines are at their maximum voltage swing. This failure mechanism is potentially an issue for any similar high-speed, high-resolution designs.

Failure Analysis of CDM-ESD Damage in a GaAs RFIC

2000 ◽  
Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Production Test ◽  
Analysis Techniques ◽  
Device Model ◽  
Charged Device ◽  
Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

2010 ◽  
Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Fault Localization ◽  
Resistance Change ◽  
The Real ◽  
Analysis Techniques ◽  
Analysis Technique ◽  
Leakage Failure ◽  
Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

Analysis of Delta Iddq Soft Fails on Pass Chips

2006 ◽  
Author(s):  
I. Österreicher ◽  
S. Eckl ◽  
B. Tippelt ◽  
S. Döring ◽  
R. Prang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mode ◽  
Photon Emission ◽  
Complete Analysis ◽  
Functional Tests ◽  
Analysis Techniques ◽  
Atomic Force ◽  
Current Consumption ◽  
Emission Microscopy ◽  
Failure Localization

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

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