Electrical Failure Analysis and Characterization of Leakage Paths Leading to Single Cell Failures in 128Mbit SDRAMs

2003 ◽  
Author(s):  
M. Versen ◽  
A. Schramm
Keyword(s):  
Failure Analysis ◽  
Single Cell ◽  
Case Studies ◽  
Leakage Current ◽  
Random Access ◽  
Electrical Failure ◽  
Leakage Path ◽  
Short Summary ◽  
Order Of Magnitude

Abstract A common failure signature in dynamic random access memories (DRAMs) is the single cell failure. The charge is lost and thereby the information stored in trench capacitors can be destroyed by high resistive leakage paths. The nature of the leakage path determines the properties of the failure such as temperature-, voltage- and timing-dependencies and its stability. In this study, high resistive leakage paths were investigated and delimited from classical shorts by estimating the order of magnitude of the leakage current and by comparison to a simple resistive leakage path. Such an investigation is the basis for a defect-based test approach that leads to multiparameter tests [1]. An introduction to the problem is given in the first section, while the second section deals with the characterization of the defects in two case studies. A short summary is given in the end.

Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages

2008 ◽  
Author(s):  
P. Schwindenhammer ◽  
H. Murray ◽  
P. Descamps ◽  
P. Poirier
Keyword(s):  
Laser Ablation ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Ablation Process ◽  
Thermally Induced ◽  
Electrical Failure ◽  
Electrical Phenomenon ◽  
Semiconductor Packages ◽  
Complex Semiconductor

Abstract Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.

Case Studies in Atomic Force Probe Analysis

2006 ◽  
Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Tony Chrastecky
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Light Emission ◽  
Electrical Characterization ◽  
Logic Circuits ◽  
Contrast Imaging ◽  
Atomic Force ◽  
Measuring Surface ◽  
Analysis Environment

Abstract The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

2020 ◽  
Author(s):  
Hyungtae Kim ◽  
Geonho Kim ◽  
Yunrong Li ◽  
Jinyong Jeong ◽  
Youngdae Kim
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
New Technology ◽  
Random Access ◽  
Analysis Data ◽  
Test Method ◽  
Design For Test ◽  
Defect Identification ◽  
Electrical Failure ◽  
Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

scholarly journals SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

2021 ◽  
Author(s):  
Hyungtae Kim ◽  
Geonho Kim ◽  
Yunrong Li ◽  
Jinyong Jeong ◽  
Youngdae Kim
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
New Technology ◽  
Random Access ◽  
Analysis Data ◽  
Test Method ◽  
Design For Test ◽  
Defect Identification ◽  
Electrical Failure ◽  
Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

scholarly journals SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

2021 ◽  
Author(s):  
Hyungtae Kim ◽  
Geonho Kim ◽  
Yunrong Li ◽  
Jinyong Jeong ◽  
Youngdae Kim
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
New Technology ◽  
Random Access ◽  
Analysis Data ◽  
Test Method ◽  
Design For Test ◽  
Defect Identification ◽  
Electrical Failure ◽  
Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

Correlation between Leakage Current and Stacking Fault Density of p-n Diodes Fabricated on 3C-SiC

2010 ◽  
Vol 645-648 ◽  
pp. 339-342 ◽  
Author(s):  
Takamitsu Kawahara ◽  
Naoki Hatta ◽  
Kuniaki Yagi ◽  
Hidetsugu Uchida ◽  
Motoki Kobayashi ◽  
...  
Keyword(s):  
Leakage Current ◽  
Current Density ◽  
Reverse Bias ◽  
Stacking Fault ◽  
Hot Electrons ◽  
Separate Paper ◽  
Fault Density ◽  
Leakage Path ◽  
Order Of Magnitude ◽  
Maximum Electric Field

The correlation between leakage current and stacking fault (SF) density in p-n diodes fabricated on 3C-SiC homo-epitaxial layer is investigated. The leakage current density at reverse bias strongly depends on the SF density; an increase of one order of magnitude in the SF density enhances the leakage current by five orders of magnitude at a reverse bias of 400 V. In order to obtain commercially suitable MOSFETs with 10-4Acm-2 at 600V, the SF density has to be reduced below 6×104 cm-2. Photoemission caused by hot electrons, which travel along a leakage path, can be observed at the crossing between a SF and the edge of p-well region; where the maximum electric field is induced. The mechanism of the leakage current is discussed in detail in a separate paper.

Single Cell Failures Caused by a Lateral Gate Effect

2004 ◽  
Author(s):  
M. Versen ◽  
A. Schramm ◽  
P. Beer ◽  
J. Lindolf
Keyword(s):  
Single Cell ◽  
Random Access ◽  
Short Introduction ◽  
The Third ◽  
Short Summary ◽  
Gate Effect ◽  
A Cell ◽  
Simulation Results ◽  
Lateral Gate ◽  
Critical Resistance

Abstract A single cell failure (SCF) is a common fail signature in dynamic random access memories (DRAMs). Generally write and read problems can be observed if a cell capacitor is not connected properly to its bitline. If the critical resistance of this connection exceeds a given threshold a failure might occur. In this analysis this threshold can be varied by a lateral gate effect of neighboring trenches. The first section gives a short introduction to the problem. An experimental analysis follows in the second section. Simulation results are presented in the third part and a short summary is given at the end.

Two Unique Case Studies Performed With Photoemission Microscopy (PEM)

1996 ◽  
Author(s):  
G.F. Shade
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Case Studies ◽  
Current Flow ◽  
Failure Mechanisms ◽  
Analysis Time ◽  
Unique Case ◽  
Qualitative Evidence ◽  
Leakage Path

Abstract Two cases are presented where photoemission microscopy (PEM) quickly reduced the analysis time by providing qualitative evidence of the suspected failure mechanisms. In both cases, the failures were delaying product shipments and the PEM technique was a "last hope" approach where other proposals were either not successful, or were not available to the analysts. In case one, package residue caused a leakage path that was located and confirmed by PEM. The second case required the use of PEM to observe uniformity of current flow within a polysilicon region. This second analysis provided absolute evidence that the current flow was nonuniform which supported the suspected failure mechanism. It is believed that this is the first reported observation of these two emission mechanisms during a failure analysis.

MBIST Driven SRAM Failure Analysis Using Laser Voltage Imaging and Laser Voltage Probing

2019 ◽  
Author(s):  
Jessica Yang ◽  
Omprakash Rengaraj ◽  
Puneet Gupta ◽  
Rudolf Schlangen
Keyword(s):  
Failure Analysis ◽  
Photon Emission ◽  
Random Access ◽  
Random Access Memory ◽  
Fault Isolation ◽  
Static Random Access Memory ◽  
Production Testing ◽  
Access Memory ◽  
Electrical Failure ◽  
Voltage Imaging

Abstract Static Random-Access Memory (SRAM) failure analysis (FA) is important during chip-level reliability evaluation and yield improvement. Single-bit, paired-bit, and quad-bit failures—whose defect should be at the failing bit-cell locations—can be directly sent for Physical Failure Analysis (PFA). For one or multiple row/column failures with too large of a suspected circuit area, more detailed fault isolation is required before PFA. Currently, Photon Emission Microscopy (PEM) is the most commonly used Electrical Failure Analysis (EFA) technique for this kind of fail [1]. Soft-Defect Localization / Dynamic Laser Stimulation (SDL/DLS) can also be applied on soft (Vmin) row/column fails for further isolation [2]. However, some failures do not have abnormal emission spots or DLS sensitivity and require different localization techniques. Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) are widely established for logic EFA, [3] but require periodic activation via ATE which may not be possible using MBIST hardware and test-patterns optimized for fast production testing. This paper discusses the test setup challenges to enable LVI & LVP on SRAM fails and includes two case studies on <14 nm advanced process silicon.

Scanning Capacitance Microscopy for Failure Analysis of SOI-Based Advanced Microprocessors

2010 ◽  
Author(s):  
Lim Soon Huat ◽  
Lwin Hnin-Ei ◽  
Vinod Narang ◽  
J.M. Chin
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
Large Area ◽  
Scanning Capacitance Microscopy ◽  
Electrical Failure ◽  
Silicon Transistors ◽  
Soi Substrates ◽  
Electrical Data

Abstract Scanning capacitance microscopy (SCM) has been used in electrical failure analysis (EFA) to isolate failing silicon transistors on silicon-on-insulator (SOI) substrates. With the shrinking device geometry and increasing layout complexity, the defects in transistors are often non-visual and require detailed electrical analysis to pinpoint the defect signature. This paper demonstrates the use of SCM technique for EFA on SOI device substrates, as well as using this technique to isolate defective contacts in a relatively large-area scan of 25µm x 25µm. We also performed dC/dV electrical characterization of defective transistors, and correlated the data from SCM technique and electrical data from nano-probing to locate failing transistors.

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