Broken Scan Chain Diagnostics Based on Time-Integrated and Time-Dependent Emission Measurements

2004 ◽  
Author(s):  
Franco Stellari ◽  
Peilin Song ◽  
Alan J. Weger ◽  
Tian Xia
Keyword(s):  
Failure Analysis ◽  
Leakage Current ◽  
Light Emission ◽  
Circuit Analysis ◽  
Time Dependent ◽  
Optical Technique ◽  
Base Method ◽  
Scan Chain

Abstract Light Emission due to Off-State Leakage Current (LEOSLC) is used in combination with the Picosecond Imaging Circuit Analysis (PICA) method to effectively diagnose and localize defects in a broken scan chain. As usual, the emission base method shows to be very effective in debugging the problem; the defect is successfully identified by the optical technique and confirmed by Physical Failure Analysis (PFA).

Non-Invasive Backside Failure Analysis of Integrated Circuits by Time-Dependent Light Emission: Picosecond Imaging Circuit Analysis

1998 ◽  
Author(s):  
J.A. Kash ◽  
J.C. Tsang ◽  
D.R. Knebel ◽  
D.P. Vallett
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Parallel Imaging ◽  
Light Emission ◽  
Logic Gate ◽  
Circuit Analysis ◽  
Back Side ◽  
Emission Data ◽  
Time Resolved ◽  
Non Invasive

Abstract A noninvasive backside probe of integrated circuits has been developed. This new probe can diagnose at-speed failures, stuck faults, and other defects. Because it is a highly parallel imaging technique, faults may be isolated which are difficult to locate by other methods. This optical technique has been named “PICA”, for picosecond imaging circuit analysis. PICA relies on the fact that an FET in a CMOS circuit emits a picosecond pulse of light each time the logic gate changes state. The source of this emission is explained. The PICA technique, which combines optical imaging of the emission with picosecond time-resolution, is described. Because of the imaging, time-resolved emission data is acquired for many transistors in parallel. The use of the emission for failure analysis and AC characterization of integrated circuits is demonstrated. Because the emission can be detected from either the front or back side of the chip, it can be used for both front and back side analysis.

Case Studies in Atomic Force Probe Analysis

2006 ◽  
Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Tony Chrastecky
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Light Emission ◽  
Electrical Characterization ◽  
Logic Circuits ◽  
Contrast Imaging ◽  
Atomic Force ◽  
Measuring Surface ◽  
Analysis Environment

Abstract The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

Failure Analysis Enhancement by Incorporating a Compact Scan Diagnosis System

2014 ◽  
Author(s):  
Rommel Estores ◽  
Pascal Vercruysse ◽  
Karl Villareal ◽  
Eric Barbian ◽  
Ralph Sanchez ◽  
...  
Keyword(s):  
Data Analysis ◽  
Failure Analysis ◽  
Real Analysis ◽  
Failure Data ◽  
Analysis Methodology ◽  
Efficiency And Effectiveness ◽  
Scan Chain ◽  
On Chip ◽  
Analysis Environment ◽  
Selection Of

Abstract The failure analysis community working on highly integrated mixed signal circuitry is entering an era where simultaneously System-On-Chip technologies, denser metallization schemes, on-chip dissipation techniques and intelligent packages are being introduced. These innovations bring a great deal of defect accessibility challenges to the failure analyst. To contend in this era while aiming for higher efficiency and effectiveness, the failure analysis environment must undergo a disruptive evolution. The success or failure of an analysis will be determined by the careful selection of tools, data and techniques in the applied analysis flow. A comprehensive approach is required where hardware, software, data analysis, traditional FA techniques and expertise are complementary combined [1]. This document demonstrates this through the incorporation of advanced scan diagnosis methods in the overall analysis flow for digital functionality failures and supporting the enhanced failure analysis methodology. For the testing and diagnosis of the presented cases, compact but powerful scan test FA Lab hardware with its diagnosis software was used [2]. It can therefore easily be combined with the traditional FA techniques to provide stimulus for dynamic fault localizations [3]. The system combines scan chain information, failure data and layout information into one viewing environment which provides real analysis power for the failure analyst. Comprehensive data analysis is performed to identify failing cells/nets, provide a better overview of the failure and the interactions to isolate the fault further to a smaller area, or to analyze subtle behavior patterns to find and rationalize possible faults that are otherwise not detected. Three sample cases will be discussed in this document to demonstrate specific strengths and advantages of this enhanced FA methodology.

Introduction of Spectral Mapping through Transmission Grating, Derivative Technique of Photon Emission

2014 ◽  
Author(s):  
Thierry Parrassin ◽  
Sylvain Dudit ◽  
Michel Vallet ◽  
Antoine Reverdy ◽  
Hervé Deslandes
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Light Emission ◽  
Photon Emission ◽  
Optical Path ◽  
Spectral Mapping ◽  
Additional Information ◽  
Transmission Grating ◽  
Emission System ◽  
Advance Knowledge

Abstract By adding a transmission grating into the optical path of our photon emission system and after calibration, we have completed several failure analysis case studies. In some cases, additional information on the emission sites is provided, as well as understanding of the behavior of transistors that are associated to the fail site. The main application of the setup is used for finding and differentiating easily related emission spots without advance knowledge in light emission mechanisms in integrated circuits.

VLSI Design for Functional Failure Analysis in the < 90 nm and Flip-Chip Era

2003 ◽  
Author(s):  
Yoav Weizman ◽  
Ezra Baruch
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Light Emission ◽  
Vlsi Design ◽  
Optical Resolution ◽  
Critical Issue ◽  
Acquisition Time ◽  
Resolution Limit ◽  
Design Rules ◽  
The Impact

Abstract In recent years, two new techniques were introduced for flip chip debug; the Laser Voltage Probing (LVP) technique and Time Resolved Light Emission Microscopy (TRLEM). Both techniques utilize the silicon’s relative transparency to wavelengths longer than the band gap. This inherent wavelength limitation, together with the shrinking dimensions of modern CMOS devices, limit the capabilities of these tools. It is known that the optical resolution limits of the LVP and TRLEM techniques are bounded by the diffraction limit which is ~1um for both tools using standard optics. This limitation was reduced with the addition of immersion lens optics. Nevertheless, even with this improvement, shrinking transistor geometry is leading to increased acquisition time, and the overlapping effect between adjacent nodes remains a critical issue. The resolution limit is an order of magnitude above the device feature densities in the &lt; 90nm era. The scaling down of transistor geometry is leading to the inevitable consequence where more than 50% of the transistors in 90nm process have widths smaller than 0.4um. The acquisition time of such nodes becomes unreasonably long. In order to examine nodes in a dense logic cuicuit, cross talk and convolution effects between neighboring signals also need to be considered. In this paper we will demonstrate the impact that these effects may have on modern design. In order to maintain the debug capability, with the currently available analytical tools for future technologies, conceptual modification of the FA process is required. This process should start on the IC design board where the VLSI designer should be familiar with FA constraints, and thus apply features that will enable enhanced FA capabilities to the circuit in hand during the electrical design or during the physical design stages. The necessity for reliable failure analysis in real-time should dictate that the designer of advanced VLSI blocks incorporates failure analysis constraints among other design rules. The purpose of this research is to supply the scientific basis for the optimal incorporation of design rules for optical probing in the &lt; 90nm gate era. Circuit designers are usually familiar with the nodes in the design which are critical for debug, and the type of measurement (logic or DC level) they require. The designer should enable the measurement of these signals by applying certain circuit and physical constraints. The implementation of these constraints may be done at the cell level, the block level or during the integration. We will discuss the solutions, which should be considered in order to mitigate tool limitations, and also to enable their use for next generation processes.

Analysis of 0.13 μm CMOS Technology Using Time Resolved Light Emission

2004 ◽  
Author(s):  
Peter Ouimet ◽  
Jason Goertz ◽  
Olivier Rinaudo ◽  
Lousinda Long ◽  
Simon Yeung
Keyword(s):  
Light Emission ◽  
Cmos Technology ◽  
Case Histories ◽  
Time Resolved ◽  
Scan Chain

Abstract This paper describes case histories of 0.13 um bulk CMOS technology analyses using Time Resolved Light Emission (TRLEM). Using this technique, scan chain, timing, and logic failures are shown to be quickly and decisively identified thereby meeting the need for rapid feedback on 1st silicon failures and process excursions.

Noise Analysis of the Leakage Current in Time-Dependent Dielectric Breakdown in a GaN SLCFET

2021 ◽  
Vol 68 (5) ◽  
pp. 2220-2225
Author(s):  
Stefano Dalcanale ◽  
Michael J. Uren ◽  
Josephine Chang ◽  
Ken Nagamatsu ◽  
Justin A. Parke ◽  
...  
Keyword(s):  
Leakage Current ◽  
Dielectric Breakdown ◽  
Noise Analysis ◽  
Time Dependent ◽  
Time Dependent Dielectric Breakdown

Yield and Failure Analysis of FinFET Source to Drain Leakage in 12nm Technology

2020 ◽  
Author(s):  
Felix Beaudoin ◽  
Satish Kodali ◽  
Rohan Deshpande ◽  
Wayne Zhao ◽  
Edmund Banghart ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Fault Localization ◽  
Detailed Characterization ◽  
Laser Stimulation ◽  
Emission Microscopy ◽  
Scan Chain ◽  
Multiple Samples ◽  
Tem Lamella ◽  
Diffusion Activation

Abstract Fault localization using both dynamic laser stimulation and emission microscopy was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nanoprobing was then performed and the source to drain leakage in N-type FinFETs was identified. After extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. This paper discusses the processes involved in yield delta datamining of FinFET and its advantages over failure characterization, fault localization, nanoprobing, and physical failure analysis.

PICA: Backside failure analysis of CMOS circuits using Picosecond Imaging Circuit Analysis

2000 ◽  
Vol 40 (8-10) ◽  
pp. 1353-1358 ◽  
Author(s):  
M.K. Mc Manus ◽  
J.A. Kash ◽  
S.E. Steen ◽  
S. Polonsky ◽  
J.C. Tsang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Circuit Analysis ◽  
Cmos Circuits
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