scholarly journals Decimation of Delta-Sigma-Modulated Signals Using a Low-Cost Microcontroller

2021 ◽  
Author(s):  
Markeljan Fishta ◽  
Franco Fiori
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Experimental Tests ◽  
General Purpose ◽  
Data Conversion ◽  
Clock Frequency ◽  
Main Challenge ◽  
Modulated Signals

Abstract$$\varDelta \varSigma $$ Δ Σ analog-to-digital converters (ADCs) are largely used in sensor acquisition applications. In the last few years, standalone $$\varDelta \varSigma $$ Δ Σ modulators have become increasingly available as off-the-shelf parts. To build a complete ADC, a standalone modulator has to be paired with some advanced elaboration unit, such as a field programmable gate array (FPGA) or a digital signal processor (DSP), which is needed for the implementation of the decimation filter. This work investigates the use of low-cost, general-purpose microcontrollers for the decimation of $$\varDelta \varSigma $$ Δ Σ -modulated signals. The main challenge is given by the clock frequency of the modulator, which can be in the range of a few $$\hbox {MHz}$$ MHz . The proposed technique deals with this limitation by employing two serial peripheral interface (SPI) modules in a time-interleaved configuration. This approach allows for continuous acquisition and elaboration of relatively high-speed, digital signals. The technique has been applied to a case study, and a data conversion system has been practically realized. The performance of the proposed filter is compared to that of a digital filter, present on board a commercial microcontroller, and the results of experimental tests are provided.

Low Power, High Speed and Area Efficient Binary Count Multiplier

2016 ◽  
Vol 25 (04) ◽  
pp. 1650027 ◽  
Author(s):  
Kore Sagar Dattatraya ◽  
Belgudri Ritesh Appasaheb ◽  
Ramdas Bhanudas Khaladkar ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
Digital Signal Processor ◽  
Word Length ◽  
High Speed ◽  
Digital Signal ◽  
General Purpose ◽  
Computation Method ◽  
Partial Product ◽  
Wallace Tree ◽  
Power Delay Product ◽  
Binary Count

Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of partial product addition by using binary adders is proposed in this paper. The binary counters for varying bit count values are derived by modifying the basic 4:2 compressor circuit. A [Formula: see text] bit multiplier has been developed to validate the proposed computation method. This logic structure demonstrates lower power operation, reduced device count and lesser delay in comparison against the conventional Wallace tree multiplier structure found in the literature. The BCM implementation realizes 29.17% reduction in the device count, 66% reduction in the delay and 70% reduction in the power dissipation. Furthermore, it realizes 90% reduction in the power delay product (PDP) in comparison against the Wallace tree structure. The multiplier circuits have been implemented and the validation of results has been carried out using Cadence[Formula: see text] EDA tool. Forty five nanometer technology files have been employed for the designs and exhaustive SPICE simulations.

An Approach to Motion Control Applications Based on Advanced Programmable Devices

2012 ◽  
Vol 49 (3) ◽  
pp. 243-259 ◽  
Author(s):  
Juvenal Rodríguez-Reséndiz ◽  
Fortino Mendoza-Mondragón ◽  
Roberto A. Gómez-Loenzo ◽  
M. Agustín Martínez-Hernández ◽  
Victor H. Mucino
Keyword(s):  
Motion Control ◽  
Digital Signal Processor ◽  
High Speed ◽  
High Performance ◽  
Engineering Students ◽  
Low Cost ◽  
Digital Signal ◽  
Hybrid Architecture ◽  
Servo Drive ◽  
Control Applications

In this article a methodology for constructing a simple servo loop for motion control applications which is suitable for educational applications is presented. The entire hardware implementation is demonstrated, focusing on a microcontroller-based (μC) servo amplifier and a field programmable gate array-digital signal processor (FPGA-DSP) motion controller. A novel hybrid architecture-based digital stage is featured providing a low-cost servo drive and a high performance controller, which can be used as a basis for an industrial application. Communication between the computer and the controller is exploited in this project in order to perform a simultaneous adaptive servo tuning. The USB protocol has been put into operation in the user front-end because a high speed sampling frequency is required for the PC to acquire position feedback signals. A software interface is developed using educational software, enabling features not only limited to a motion profile but also the supervisory control and data acquisition (SCADA) topology of the system. A classical proportional-integral-derivative controller (PID) is programmed on a DSP in order to ensure a proper tracking of the reference at both low and high speeds in a d.c. motor. Furthermore, certain blocks are embedded on an FPGA. As a result, three of the most important technologies in signal processing are featured, permitting engineering students to understand several concepts covered in theoretical courses.

Novel Discrete Components Based Speed Controller for Induction Motor

2016 ◽  
Vol 7 (4) ◽  
pp. 1075
Author(s):  
Hussain Attia ◽  
Ali Sagafinia
Keyword(s):  
Induction Motor ◽  
Digital Signal Processor ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Digital Signal ◽  
Speed Control ◽  
Electronic System ◽  
Voltage Controlled Oscillator ◽  
Electronic Design

This paper presents an electronic design based on general purpose discrete components for speed control of a single phase induction motor drive. The MOSFETs inverter switching is controlled using Sampled Sinusoidal Pulse Width Modulation (SPWM) techniques with V/F method based on Voltage Controlled Oscillator (VCO). The load power is also controlled by a novel design to produce a suitable SPWM pulse. The proposed electronic system has ability to control the output frequency with flexible setting of lower limit to less than 1 Hz and to higher frequency limits to 55 Hz. Moreover, the proposed controller able to control the value of load voltage to frequency ratio, which plays a major parameter in the function of IM speed control. Furthermore, the designed system is characterized by easy manufacturing and maintenance, high speed response, low cost, and does not need to program steps as compared to other systems based on Microcontroller and digital signal processor (DSP) units. The complete proposed electronic design is made by the software of NI Multisim version 11.0 and all the internal sub-designs are shown in this paper. Simulation results show the effectiveness of electronic design for a promising of a high performance IM PWM drive.

scholarly journals Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 243 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Douglas Maskell ◽  
Nikos Mastorakis
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Cmos Technology ◽  
General Purpose ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Cycle

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

scholarly journals A Review of Self-Coherent Optical Transceivers: Fundamental Issues, Recent Advances, and Research Directions

2021 ◽  
Vol 11 (16) ◽  
pp. 7554
Author(s):  
Isiaka Alimi ◽  
Romil Patel ◽  
Nuno Silva ◽  
Chuanbowen Sun ◽  
Honglin Ji ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Dynamic Environment ◽  
Digital Signal ◽  
Research Directions ◽  
Recent Advances ◽  
Heterogeneous Nature ◽  
Signal Processing Algorithms ◽  
Processing Algorithms

This paper reviews recent progress on different high-speed optical short- and medium-reach transmission systems. Furthermore, a comprehensive tutorial on high-performance, low-cost, and advanced optical transceiver (TRx) paradigms is presented. In this context, recent advances in high-performance digital signal processing algorithms and innovative optoelectronic components are extensively discussed. Moreover, based on the growing increase in the dynamic environment and the heterogeneous nature of different applications and services to be supported by the systems, we discuss the reconfigurable and sliceable TRxs that can be employed. The associated technical challenges of various system algorithms are reviewed, and we proffer viable solutions to address them.

Low Noise EEG Amplifier Board for Low Cost Wearable BCI Devices

2016 ◽  
Vol 5 (2) ◽  
pp. 17-28
Author(s):  
Ravim ◽  
Suma K. V.
Keyword(s):  
Noise Reduction ◽  
Digital Signal Processor ◽  
Low Cost ◽  
Processing System ◽  
Digital Signal ◽  
Low Noise ◽  
Digital Data ◽  
Signal Processing System ◽  
Analog To Digital ◽  
Reduction Techniques

Designing a real-time BCI device requires an Electroencephalogram (EEG) acquisition system and a signal processing system to process that acquired data. EEG acquisition boards available in market are expensive and they are required to be connected to computer for any processing work. Various low cost Digital Signal Processor (DSP) boards available in market come with internal Analog to Digital converters and peripheral interfaces. The idea is to design a low cost EEG amplifier board that can be used with these commercially available DSP boards. The analog data from EEG amplifier can be converted to digital data by DSP board and sent to computer via an interface for algorithm development and further control operations. EEG amplifiers are highly affected by noise from environment. Proper noise reduction techniques are implemented and simulated in circuit design. Each filter stage and noise reduction circuit is evaluated for a low noise design.

scholarly journals Detection and control of a gyroscopically induced vibration to improve the balance of a single-wheel robot

2017 ◽  
Vol 37 (3) ◽  
pp. 443-455 ◽  
Author(s):  
Sangdeok Lee ◽  
Seul Jung
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Balance Control ◽  
A Priori ◽  
Experimental Studies ◽  
Notch Filter ◽  
Digital Signal ◽  
Control Performance ◽  
And Control ◽  
Balancing Control

In this article, an experimental investigation of the detection of a gyroscopically induced vibration and the balancing control performance of a single-wheel robot is presented. The balance of the single-wheel robot was intended to be maintained by virtue of the gyroscopic effect induced from a highly rotating flywheel. Since the flywheel rotates at a high speed, an asymmetrical structure of a flywheel causes an irregular rotation and becomes one of the major vibration sources. A vibration was detected and suppressed a priori before applying control algorithms to the robot. Gyroscopically induced vibrations can empirically be detected with different rotational velocities. The detection of the balancing angle of the single-wheel robot was accomplished by using an attitude and heading reference system. After identifying the vibrating frequencies, a notch filter was designed to suppress the vibration at the typical frequencies identified through experiments. A digital filter was designed and implemented in a digital signal processor(DSP) along with the control scheme for the balance control performance. The performance of the proposed method was verified by the experimental studies on the balancing control of the single-wheel robot. Experimental results confirmed that the notch filter designed following the detection of the flywheel’s vibration actually improved the balancing control performance. A half of the vibration magnitude was reduced by the proposal.

A High Speed 8B/10B Encoder/Decoder Design Based on Low Cost FPGA

2012 ◽  
Vol 462 ◽  
pp. 361-367 ◽  
Author(s):  
Zhang Jin Chen ◽  
Guo Hai Zhong ◽  
Zhuo Bi
Keyword(s):  
High Speed ◽  
Single Channel ◽  
Low Cost ◽  
Maximum Frequency ◽  
Clock Frequency ◽  
Parallel Pipeline ◽  
Quartus Ii ◽  
Simulation Results ◽  
Decoder Design ◽  
Timing Simulation

A high speed 8B/10B Encoder/Decoder is presented in this paper. The Encoder/Decoder is based on Altera’s low cost FPGA Cyclone family. The Encoder/Decoder includes parallel pipeline structure. The Encoder/Decoder is applied to the Serializer/Deserializer (SERDES) of high-speed serial bus. The Encoder/Decoder is synthesized and simulated by Quartus II 9.1. The synthesis and analysis results show the maximum frequency is more than 359MHz. The timing simulation results show the clock frequency is more than 125 MHz. The single channel data rate of serial bus can get to 1.25Gbps. The proposed Encoder/Decoder can meet the requirements of most high-speed serial bus.

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