A High Speed 8B/10B Encoder/Decoder Design Based on Low Cost FPGA

2012 ◽  
Vol 462 ◽  
pp. 361-367 ◽  
Author(s):  
Zhang Jin Chen ◽  
Guo Hai Zhong ◽  
Zhuo Bi
Keyword(s):  
High Speed ◽  
Single Channel ◽  
Low Cost ◽  
Maximum Frequency ◽  
Clock Frequency ◽  
Parallel Pipeline ◽  
Quartus Ii ◽  
Simulation Results ◽  
Decoder Design ◽  
Timing Simulation

A high speed 8B/10B Encoder/Decoder is presented in this paper. The Encoder/Decoder is based on Altera’s low cost FPGA Cyclone family. The Encoder/Decoder includes parallel pipeline structure. The Encoder/Decoder is applied to the Serializer/Deserializer (SERDES) of high-speed serial bus. The Encoder/Decoder is synthesized and simulated by Quartus II 9.1. The synthesis and analysis results show the maximum frequency is more than 359MHz. The timing simulation results show the clock frequency is more than 125 MHz. The single channel data rate of serial bus can get to 1.25Gbps. The proposed Encoder/Decoder can meet the requirements of most high-speed serial bus.

Dynamic behaviors of a high-speed turbocharger rotor on elliptical floating-ring bearings

2019 ◽  
Vol 233 (12) ◽  
pp. 1785-1799 ◽  
Author(s):  
Congcong Zhang ◽  
Yongliang Wang ◽  
Rixiu Men ◽  
Hong He ◽  
Wei Chen
Keyword(s):  
High Speed ◽  
Reynolds Equation ◽  
Low Cost ◽  
Dynamic Behaviors ◽  
Oil Whirl ◽  
Excited Vibration ◽  
Dynamic Performances ◽  
Simulation Results ◽  
Bearing Design ◽  
Run Up

Floating-ring bearings are commonly used in automotive turbocharger applications due to their low cost and their suitability under extreme rotation speeds. This type of bearings, however, can become a source of noise due to oil whirl-induced sub-synchronous vibrations. The scope of this paper is to examine whether the concept of a floating-ring bearing with an elliptical clearance might be a solution to suppress sub-synchronous vibrations. A very time-efficient approximate solution for the Reynolds equation to the geometry of elliptical bearings is presented. The nonlinear dynamic behaviors of a turbocharger rotor supported by two concepts of elliptical floating-ring bearings are systematically investigated using run-up simulations. For the first concept of elliptical floating-ring bearings i.e. the outer bearing of the floating-ring bearing changed in the form of elliptical pattern (see Figure 1(b) in the article), some studies have pointed out that its steady-state and dynamic performances are superior to plain cylindrical floating-ring bearings but, the nonlinear run-up simulation results shown that this type of elliptical floating-ring bearings is not conducive to reduce the self-excited vibration levels. However, for the second type of elliptical floating-ring bearings i.e. both the inner and outer films of the floating-ring bearing changed in the form of elliptical pattern (see Figure 1(c) in the article), it is shown that the sub-synchronous vibrations have been considerably suppressed. Hence, the second noncircular floating-ring bearing design is an attractive measure to suppress self-excited vibrations.[Figure: see text]

scholarly journals Decimation of Delta-Sigma-Modulated Signals Using a Low-Cost Microcontroller

2021 ◽  
Author(s):  
Markeljan Fishta ◽  
Franco Fiori
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Experimental Tests ◽  
General Purpose ◽  
Data Conversion ◽  
Clock Frequency ◽  
Main Challenge ◽  
Modulated Signals

Abstract$$\varDelta \varSigma $$ Δ Σ analog-to-digital converters (ADCs) are largely used in sensor acquisition applications. In the last few years, standalone $$\varDelta \varSigma $$ Δ Σ modulators have become increasingly available as off-the-shelf parts. To build a complete ADC, a standalone modulator has to be paired with some advanced elaboration unit, such as a field programmable gate array (FPGA) or a digital signal processor (DSP), which is needed for the implementation of the decimation filter. This work investigates the use of low-cost, general-purpose microcontrollers for the decimation of $$\varDelta \varSigma $$ Δ Σ -modulated signals. The main challenge is given by the clock frequency of the modulator, which can be in the range of a few $$\hbox {MHz}$$ MHz . The proposed technique deals with this limitation by employing two serial peripheral interface (SPI) modules in a time-interleaved configuration. This approach allows for continuous acquisition and elaboration of relatively high-speed, digital signals. The technique has been applied to a case study, and a data conversion system has been practically realized. The performance of the proposed filter is compared to that of a digital filter, present on board a commercial microcontroller, and the results of experimental tests are provided.

A modified Fresnel-based algorithm for 3D microwave imaging of metal objects

2018 ◽  
Vol 11 (4) ◽  
pp. 313-325
Author(s):  
Farshad Zamiri ◽  
Abdolreza Nabavi
Keyword(s):  
High Speed ◽  
Fourier Transforms ◽  
Low Cost ◽  
Three Dimensional ◽  
Computation Time ◽  
Microwave Imaging ◽  
Reconstruction Algorithms ◽  
Clock Frequency ◽  
Pipeline Architecture ◽  
The Impact

AbstractMicrowave holography technique reconstructs a target image using recorded amplitudes and phases of the signals reflected from the target with Fast Fourier Transform (FFT)-based algorithms. The reconstruction algorithms have two or more steps of two- and three-dimensional Fourier transforms, which have a high computational load. In this paper, by neglecting the impact of target depth on image reconstruction, an efficient Fresnel-based algorithm is proposed, involving only one-step FFT for both single- and multi-frequency microwave imaging. Numerous tests have been performed to show the effectiveness of the proposed algorithm including planar and non-planar targets, using the raw data gathered by means of a scanner operating in X-band. Finally, a low-cost and high-speed hardware architecture based on fixed-point arithmetic is introduced which reconstructs the planar targets. This pipeline architecture was tested on field programmable gate arrays operating at 200 MHz clock frequency, which illustrates more than 30 times improvement in computation time compared with a computer.

Research and Design of Beamforming Device of SLC-LSCMA Algorithm Based on FPGA

2013 ◽  
Vol 347-350 ◽  
pp. 1677-1681
Author(s):  
Qing Fang Zhou ◽  
Yan Yan Yu ◽  
Lei Wang ◽  
Jun Yang
Keyword(s):  
Least Squares ◽  
Satellite Communications ◽  
Clock Frequency ◽  
Verilog Hdl ◽  
Description Language ◽  
Quartus Ii ◽  
Hardware Description ◽  
Timing Simulation ◽  
Array Beamforming ◽  
Research And Design

In this paper,we design a uniform circular array beamforming device of 16 yuan based on the least squares SLC-LSCMA algorithm (based on the linear subspace constrained least squares cma) high stability and rapid convergence for the foundation. The design of the complete beam-forming the SLC-LSCMA algorithm by plural, time-multiplier and accumulators, which uses less resources and faster than the traditional algorithm. The beamforming device uses hardware description language of Verilog HDL , and wires on the QUARTUS II 8.0. Finally the beamforming device is downloaded to the Alteras EP2C35F672C6, and its timing simulation can be run properly in the 50MHz clock frequency. This design can be widely used in mobile communication and satellite communications.

A Low-Noise Dynamic Comparator with Offset Calibration for CMOS Image Sensor Architecture

2018 ◽  
Vol 28 (02) ◽  
pp. 1950022
Author(s):  
Arumugam Sathishkumar ◽  
Siddhan Saravanan
Keyword(s):  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Low Noise ◽  
Clock Frequency ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Input Capacitance ◽  
Simulation Results ◽  
Output Swing

A low-noise, high-speed, low-input-capacitance switched dynamic comparator (SDC) CMOS image sensor architecture is presented in this paper. The comparator design occupying less area and consuming lesser power is suitable for bank of comparators in CMOS image readouts. The proposed dynamic comparator eliminates the stacking issue related to the conventional comparator and reduces the offset noise further. The need for low-noise, low-power, area-efficient and high-speed flash analog-to-digital converters (ADCs) in many applications today motivated us to design a comparator for ADC. The rail-to-rail output swing is also improved. The input capacitance is reduced by using shared first-stage technique. The comparator is designed with constant [Formula: see text]/[Formula: see text] biasing to suppress the environmental drift. The simulation results from 45-nm and 65-nm CMOS technologies confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 3.5[Formula: see text]GHz and 2.2[Formula: see text]GHz at supply voltages of 1[Formula: see text]V and 0.6[Formula: see text]V, respectively. Simulations are carried out using predictive technology models for 45[Formula: see text]nm and 65[Formula: see text]nm in HSPICE.

scholarly journals A New Approach for Eye-Blink to Speech Conversion by Dynamic Time Warping

2021 ◽  
Vol 38 (2) ◽  
pp. 369-377
Author(s):  
Güneş Ekim ◽  
Ayten Atasoy ◽  
Nuri İkizler
Keyword(s):  
Environmental Factors ◽  
Dynamic Time Warping ◽  
High Speed ◽  
Single Channel ◽  
Low Cost ◽  
High Accuracy ◽  
Eye Tracker ◽  
Time Warping ◽  
Eye Blink ◽  
Dynamic Time

Motor neuron patients such as paralysis, locking syndrome, and amyotrophic lateral sclerosis can see and hear what is happening in their environment, but cannot communicate with their environment. It is very important for these patients, who do not have any physical function other than eye movements, to be able to express their needs, feelings and thoughts. Therefore, to express the thoughts, needs and feelings of these patients, a system that converts eye-blink signals to speech was developed in this study. The main purpose of the designed system is high accuracy, low cost, high speed and independence from environmental factors. Undoubtedly, it is also very important that it causes as little discomfort to the patient as possible. Morse-coded signals generated by voluntary eye-blinks and the single-channel wireless NeuroSky MindWave Mobile device eliminates the need for cost-increasing equipment such as a camera or eye tracker and environmental factors such as light. With the use of Dynamic Time Warping (DTW), an algorithm which works at high speed and high accuracy at the time domain and does not require any training process has been implemented. In this way, the recorded speech was performed with a quite impressive accuracy.

scholarly journals A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4715
Author(s):  
Wei He ◽  
Jinguo Huang ◽  
Tengxiao Wang ◽  
Yingcheng Lin ◽  
Junxian He ◽  
...  
Keyword(s):  
Online Learning ◽  
High Speed ◽  
Low Cost ◽  
High Energy ◽  
Training Procedure ◽  
Vision Sensor ◽  
Clock Frequency ◽  
Dynamic Vision ◽  
Vlsi System ◽  
On Chip

This paper proposes a high-speed low-cost VLSI system capable of on-chip online learning for classifying address-event representation (AER) streams from dynamic vision sensor (DVS) retina chips. The proposed system executes a lightweight statistic algorithm based on simple binary features extracted from AER streams and a Random Ferns classifier to classify these features. The proposed system’s characteristics of multi-level pipelines and parallel processing circuits achieves a high throughput up to 1 spike event per clock cycle for AER data processing. Thanks to the nature of the lightweight algorithm, our hardware system is realized in a low-cost memory-centric paradigm. In addition, the system is capable of on-chip online learning to flexibly adapt to different in-situ application scenarios. The extra overheads for on-chip learning in terms of time and resource consumption are quite low, as the training procedure of the Random Ferns is quite simple, requiring few auxiliary learning circuits. An FPGA prototype of the proposed VLSI system was implemented with 9.5~96.7% memory consumption and <11% computational and logic resources on a Xilinx Zynq-7045 chip platform. It was running at a clock frequency of 100 MHz and achieved a peak processing throughput up to 100 Meps (Mega events per second), with an estimated power consumption of 690 mW leading to a high energy efficiency of 145 Meps/W or 145 event/μJ. We tested the prototype system on MNIST-DVS, Poker-DVS, and Posture-DVS datasets, and obtained classification accuracies of 77.9%, 99.4% and 99.3%, respectively. Compared to prior works, our VLSI system achieves higher processing speeds, higher computing efficiency, comparable accuracy, and lower resource costs.

BENCHMARK RESULTS FOR HIGH-SPEED 4-BIT ACCUMULATORS IMPLEMENTED IN INDIUM PHOSPHIDE DHBT TECHNOLOGY

2004 ◽  
Vol 14 (03) ◽  
pp. 646-651 ◽  
Author(s):  
STEVEN EUGENE TURNER ◽  
DAVID E. KOTECKI
Keyword(s):  
Indium Phosphide ◽  
Power Consumption ◽  
High Speed ◽  
Large Scale ◽  
Supply Voltage ◽  
Power Reduction ◽  
Test Results ◽  
Clock Frequency ◽  
Speed Performance ◽  
Simulation Results

High-speed accumulators are frequently used as a benchmark of the high-speed performance and ability to yield large scale circuits in InP double hetereojunction bipolar (DHBT) processes. In previous work, we reported test results of an InP DHBT 4-bit accumulator with 624 transistors operating at 41 GHz clock frequency with a power consumption of 4.1W. In this work, we report on modifications that allow the circuit to operate at a lower supply voltage and a corresponding lower power consumption. Simulation results for this modification indicate that a 16% power reduction can be obtained, while maintaining a high-speed operating frequency of 40 GHz.

scholarly journals A High-Speed and Low-Offset Dynamic Latch Comparator

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Labonnah Farzana Rahman ◽  
Mamun Bin Ibne Reaz ◽  
Chia Chieu Yin ◽  
Mohammad Marufuzzaman ◽  
Mohammad Anisur Rahman
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Offset Voltage ◽  
Simulation Results ◽  
Low Offset

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of148.80 μm×59.70 μm.

FPGA Implementation of Fast and Efficient CODEC for H.264/AVC Real Time Video Applications

2016 ◽  
Vol 7 (1) ◽  
pp. 32-52
Author(s):  
Yasser Ismail
Keyword(s):  
Motion Estimation ◽  
Real Time ◽  
High Speed ◽  
Low Cost ◽  
Bit Rate ◽  
Power Networks ◽  
Time Saving ◽  
Device Processing ◽  
Simulation Results ◽  
Iot Devices

Low power networks are considered nowadays as a fundamental environment for connecting and communicating various “things.” Such connected things form the hot topic Internet-of-Things (IoT) that emphasizes on better and smarter interconnected world. The two main important issues raised in the IoT are the transmitted bit-rate and the device processing capability limitations. In this paper, a smart Skipping Motion Estimation threshold (TSME) is implemented and elaborated to match the processing capabilities of the IoT devices. The proposed threshold aims to achieve a great reduction in the computations of the Motion Estimation (ME) process with acceptable bit-rate and high speed that are suitable for real time video applications. Simulation results show that there is great reductions in the computations represented by the Motion Estimation Time Saving percentage (METS%) up to 51% and 49% in case of using average and median functions, respectively. Implementation results of the proposed threshold unit on an FPGA show low cost hardware with a maximum hardware frequency of 379.140MHz.

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