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An analysis on the ambipolar current in Si double-gate tunnel FETs
Solid-State Electronics
◽
10.1016/j.sse.2011.11.009
◽
2012
◽
Vol 70
◽
pp. 67-72
◽
Cited By ~ 115
Author(s):
Hraziia
◽
Andrei Vladimirescu
◽
Amara Amara
◽
Costin Anghel
Keyword(s):
Double Gate
◽
Ambipolar Current
◽
Tunnel Fets
Download Full-text
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Cited By
References
Controlling the ambipolar current in ultrathin SOI tunnel FETs using the back-bias effect
Journal of Computational Electronics
◽
10.1007/s10825-020-01484-8
◽
2020
◽
Vol 19
(2)
◽
pp. 658-667
◽
Cited By ~ 3
Author(s):
Tripuresh Joshi
◽
Balraj Singh
◽
Yashvir Singh
Keyword(s):
Bias Effect
◽
Ambipolar Current
◽
Tunnel Fets
◽
Ultrathin Soi
Download Full-text
Influence of Localized Interface Charges on Drain Current of Dual-Material Double-Gate Tunnel FETs
2018 3rd International Conference for Convergence in Technology (I2CT)
◽
10.1109/i2ct.2018.8529418
◽
2018
◽
Author(s):
Sanjay Kumar
◽
Kamlaksha Baral
◽
Sweta Chander
◽
P. K. Singh
◽
Kunal Singh
◽
...
Keyword(s):
Drain Current
◽
Double Gate
◽
Interface Charges
◽
Tunnel Fets
◽
Dual Material
Download Full-text
Performance of asymmetric gate oxide on gate-drain overlap in Si and Si1−xGex double gate tunnel FETs
2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)
◽
10.1109/vlsi-sata.2016.7593036
◽
2016
◽
Author(s):
S. Poorvasha
◽
B. Lakshmi
Keyword(s):
Gate Oxide
◽
Double Gate
◽
Tunnel Fets
Download Full-text
Dual-Metal Graded-Channel Double-Gate Tunnel FETs for Reduction of Ambipolar Conduction
2018 IEEE Electron Devices Kolkata Conference (EDKCON)
◽
10.1109/edkcon.2018.8770449
◽
2018
◽
Cited By ~ 3
Author(s):
Chandan K. Pandey
◽
Saurabh Chaudhury
Keyword(s):
Double Gate
◽
Tunnel Fets
◽
Dual Metal
◽
Ambipolar Conduction
Download Full-text
Double-gate Ge, In As-based tunnel FETs with enhanced ON-current
2016 International Conference on Communication and Signal Processing (ICCSP)
◽
10.1109/iccsp.2016.7754219
◽
2016
◽
Cited By ~ 2
Author(s):
Chebrolu Gopi
◽
Sudakar Singh Chauhan
Keyword(s):
Double Gate
◽
Tunnel Fets
Download Full-text
Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs
Japanese Journal of Applied Physics
◽
10.7567/1347-4065/ab6569
◽
2020
◽
Vol 59
(SG)
◽
pp. SGGA06
Author(s):
Koichi Fukuda
◽
Naoya Nogami
◽
Shogo Kunisada
◽
Yasuyuki Miyamoto
Keyword(s):
Double Gate
◽
Device Design
◽
Design Scheme
◽
Tunnel Fets
Download Full-text
Investigation of geometrical and doping parameter variations on GaSb/Si‐based double gate tunnel FETs: A qualitative and quantitative approach for RF performance enhancement
International Journal of Numerical Modelling Electronic Networks Devices and Fields
◽
10.1002/jnm.2633
◽
2019
◽
Vol 32
(6)
◽
Author(s):
Poorvasha Shanmuganathan
◽
Lakshmi Balasubramanian
Keyword(s):
Performance Enhancement
◽
Quantitative Approach
◽
Double Gate
◽
Qualitative And Quantitative
◽
Parameter Variations
◽
Tunnel Fets
◽
Rf Performance
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Compact modeling of intrinsic capacitances in Double-Gate Tunnel-FETs
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
◽
10.1109/ulis.2017.7962584
◽
2017
◽
Cited By ~ 3
Author(s):
A. Farokhnejad
◽
M. Graef
◽
F. Horst
◽
C. Liu
◽
Q.T. Zhao
◽
...
Keyword(s):
Compact Modeling
◽
Double Gate
◽
Tunnel Fets
Download Full-text
Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis
IEEE Access
◽
10.1109/access.2019.2936610
◽
2019
◽
Vol 7
◽
pp. 117591-117599
◽
Cited By ~ 2
Author(s):
Shelly Garg
◽
Sneh Saurabh
Keyword(s):
Double Gate
◽
Tunnel Fets
◽
Logic Functions
Download Full-text
Two-dimensional bias dependent model for the screening length in double-gate Tunnel-FETs
2013 14th International Conference on Ultimate Integration on Silicon (ULIS)
◽
10.1109/ulis.2013.6523483
◽
2013
◽
Cited By ~ 1
Author(s):
M. Graef
◽
M. Schwarz
◽
T. Holtij
◽
F. Hain
◽
A. Kloes
◽
...
Keyword(s):
Double Gate
◽
Two Dimensional
◽
Screening Length
◽
Dependent Model
◽
Tunnel Fets
Download Full-text
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