Research on COB-LED light source with tunable CCT based on screen printing and flip chip technology

2022 ◽  
Vol 54 (2) ◽  
Author(s):  
Rongrong Zhang ◽  
Zuojie Wen ◽  
Bingqian Li ◽  
Shenghua Liang ◽  
Mingde Yang ◽  
...  
2021 ◽  
Author(s):  
Rongrong Zhang ◽  
Zuojie Wen ◽  
Bingqian Li ◽  
Shenghua Liang ◽  
Mingde Yang ◽  
...  

Abstract Using the characteristic of flip light emitting diode (LED) chips without front-side welding wires, before applying fluorescent glue throughout the luminous surface, a part of the chips are directionally and quantitatively coated fluorescent glue by screen printing process, a chip on board (COB) white LED light source is developed with adjustable correlated color temperature (CCT). A part of the blue LED chips in the light source excites the fluorescent glue to produce a warm white light (CCT = 2631K), and the other part produces cool white light (CCT = 6181K). When changing the driving current ratio of the two parts of the chips, the CCT of COB LED light source can be continuously adjusted between warm and cool white light. According to the measured data, the relationship between the CCT and the driving current ratio of the two parts is obtained by fitting. Within the adjustable range of the CCT (2631 K to 6181 K), the color rendering index (CRI) is about 90. The minimum is 89.3 and the maximum is 93.1. While achieving adjustable CCT and high CRI, the LED light source has a luminous flux of 1938.76 lm on a circular surface with a diameter of 11 mm. The overall luminous efficiency is close to 100 lm/W.


2009 ◽  
Vol 12 (1) ◽  
pp. 72-78 ◽  
Author(s):  
Satoshi Fujii ◽  
Takeshi Fukui ◽  
Yuji Uchida ◽  
Satoshi Kurai ◽  
Tsunemasa Taguchi

Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.


Author(s):  
O. Diaz de Leon ◽  
M. Nassirian ◽  
C. Todd ◽  
R. Chowdhury

Abstract Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.


2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.


2021 ◽  
Vol 11 (9) ◽  
pp. 4035
Author(s):  
Jinsheon Kim ◽  
Jeungmo Kang ◽  
Woojin Jang

In the case of light-emitting diode (LED) seaport luminaires, they should be designed in consideration of glare, average illuminance, and overall uniformity. Although it is possible to implement light distribution through auxiliary devices such as reflectors, it means increasing the weight and size of the luminaire, which reduces the feasibility. Considering the special environment of seaport luminaires, which are installed at a height of 30 m or more, it is necessary to reduce the weight of the device, facilitate replacement, and secure a light source with a long life. In this paper, an optimized lens design was investigated to provide uniform light distribution to meet the requirement in the seaport lighting application. Four types of lens were designed and fabricated to verify the uniform light distribution requirement for the seaport lighting application. Using numerical analysis, we optimized the lens that provides the required minimum overall uniformity for the seaport lighting application. A theoretical analysis for the heatsink structure and shape were conducted to reduce the heat from the high-power LED light sources up to 250 W. As a result of these analyses on the heat dissipation characteristics of the high-power LED light source used in the LED seaport luminaire, the heatsink with hexagonal-shape fins shows the best heat dissipation effect. Finally, a prototype LED seaport luminaire with an optimized lens and heat sink was fabricated and tested in a real seaport environment. The light distribution characteristics of this prototype LED seaport luminaire were compared with a commercial high-pressure sodium luminaire and metal halide luminaire.


Author(s):  
Peian Li ◽  
Xu Zhang ◽  
Wing Cheung Chong ◽  
Kei May Lau

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