A Low-Voltage and Low-Power 3-GHz CMOS LC VCO for S-Band Wireless Applications

2014 ◽  
Vol 78 (2) ◽  
pp. 905-914 ◽  
Author(s):  
Fei Yu
Frequenz ◽  
2014 ◽  
Vol 68 (11-12) ◽  
Author(s):  
Shiqiang Chen ◽  
Junfeng Wang

AbstractThis paper describes a low voltage low power (LV-LP) folded mixer for S-band wireless applications. The proposed mixer could convert a 10 MHz intermediate frequency (IF) signal to a 2.4 GHz RF signal with a local oscillator (LO) power of 0 dBm at 2.39 GHz. The comparison with the previous reported mixers shows that the proposed mixer has the advantages of lower voltage, lower power consumption and higher conversion gain than most of the other works. Simulation results demonstrate that the mixer a remarkable conversion gain of 10.5 dB while consuming only 0.65 mW DC power from a 0.8 V supply voltage. The input-referred third-order intercept point (IIP3) of the mixer is 3.75 dBm, and the chip area is only 0.525 mm


Author(s):  
Shitesh Tiwari ◽  
Sumant Katiyal ◽  
Parag Parandkar

Voltage Controlled Oscillator (VCO) is an integral component of most of the receivers such as GSM, GPS etc. As name indicates, oscillation is controlled by varying the voltage at the capacitor of LC tank. By varying the voltage, VCO can generate variable frequency of oscillation. Different VCO Parameters are contrasted on the basis of phase noise, tuning range, power consumption and FOM. Out of these phase noise is dependent on quality factor, power consumption, oscillation frequency and current. So, design of LC VCO at low power, low phase noise can be obtained with low bias current at low voltage.  Nanosize transistors are also contributes towards low phase noise. This paper demonstrates the design of low phase noise LC VCO with 4.89 GHz tuning range from 7.33-11.22 GHz with center frequency at 7 GHz. The design uses 32nm technology with tuning voltage of 0-1.2 V. A very effective Phase noise of -114 dBc / Hz is obtained with FOM of -181 dBc/Hz. The proposed work has been compared with five peer LC VCO designs working at higher feature sizes and outcome of this performance comparison dictates that the proposed work working at better 32 nm technology outperformed amongst others in terms of achieving low Tuning voltage and moderate FoM, overshadowed by a little expense of power dissipation. 


2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).


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