Advances in microelectronic processing

JOM ◽  
2001 ◽  
Vol 53 (6) ◽  
pp. 42-42
Author(s):  
N. M. Ravindra ◽  
A. Kumar
MRS Advances ◽  
2017 ◽  
Vol 2 (57) ◽  
pp. 3537-3546 ◽  
Author(s):  
Delphine Dean ◽  
Katherine Hafner ◽  
Xue Chen ◽  
Brian Kirkland ◽  
Theresa Hafner ◽  
...  

ABSTRACTDetermining what external stimuli influence cell differentiation, morphology, and growth continues to be a focus on many research groups to meet the healthcare Grand Challenges. While prior work has shown the influence of stiffness, surface chemistry and topography, these parameters often change in tandem, making it difficult to delineate the role of an individual component. This study examined the possible incorporation of microelectronic processing to produce reusable substrates for cell guidance studies. Subsequent plating of substrates cleaned with methods common in a microelectronic fabrication process showed complex responses including migration. Optical characterization of surfaces after cleaning showed remaining cellular debris that could be removed through the incorporation of a piranha solution. The micro patterned substrates did allow controlled comparison between dental pulp stem cells and osteoblast cells. The dental pulp cells did not show any cell alignment or cell proliferation (as indicated by cell density) with the isotropic or anisotropic micropatterns on the initial plating. The osteoblast cells (control) only aligned with the lines and not any of the other patterns (dots, holes or hexagons).


1996 ◽  
Vol 452 ◽  
Author(s):  
L. Tsybeskov ◽  
K. D. Hirschman ◽  
S. P. Duttagupta ◽  
P. M. Fauchet

AbstractLEDs based on silicon-rich silicon oxide (SRSO) have been fabricated utilizing thermal oxidation of electrochemically etched c-Si and standard microelectronic processes including LPCVD, photolithography, ion implantation and metallization. The bipolar devices consist of heavily-doped polycrystalline Si, a transition layer made of oxidized mesoporous Si, an active SRSO layer (doped or intrinsic) and a crystalline Si substrate. The LED's electrical properties exhibit a low interface state density which is explained by the partial filling of the micropores within the transition layer by polycrystalline Si. The dominant carrier transport in SRSO is due to thermally-assisted tunneling at low fields and electric field-assisted (Fowler-Nordheim) tunneling at high fields. The electroluminescence (EL) is stable and the EL modulation is limited by the carrier transition time (not by the carrier lifetime) which explains the high modulation speed (≥ 10 MHz). We have fabricated a prototype alphanumeric 7-segment display with an isolated version of the LEDs and standard microelectronic processing techniques.


1999 ◽  
Vol 565 ◽  
Author(s):  
J. M. Snodgrass ◽  
D. Pantelidis ◽  
J. C. Bravman ◽  
R. H. Dauskardt

AbstractThe adhesion of thin film polymers will be critical in the integration of low-κ materials into microelectronic processing. This study describes the adhesion of two promising low-κ polymers (polyimide and benzocyclobutene) to a silicon dioxide surface. Critical adhesion values were measured using interface fracture mechanics samples in a double cantilever beam geometry. The effect of subcritical (time-dependent) delamination was also evaluated for these systems. Subcritical debonding data are important in understanding the effect of environment and temperature on interface reliability. To that end, experiments were conducted over a range of humidities to elucidate the effect of moisture on interface delamination. The important effect of the acceleration of debond growth rates due to cyclic loading is also described. In addition, XPS studies are presented to characterize the debond path in these layered systems.


1995 ◽  
Vol 402 ◽  
Author(s):  
P. E. Hompson ◽  
M. Weeks ◽  
P. Tedrow ◽  
K. Hobart

AbstractEncouraging results have been reported for discrete heterojunction internal photoemission (HIP) infrared (IR) detectors composed of heavily boron doped Si1−3Gex layers on Si. We desired to build on those results and fabricate 640×480 IR focal plane arrays on 100 mm Si substrates, suitable for commercial microelectronic processing. In this paper we discuss the growth issues for growing these structures by molecular beam epitaxy. Since the wafers had already undergone processing and some had PtSi contacts, the growth temperature was constrained to be no greater than 600 °C. Precise temperature control was obtained by calibrating an optical pyrometer with a thermocouple embedded in the substrate heater assembly, which was calibrated using the eutectic emperatures of Au/Si and Al/Si. The final step of the cleaning process was a 1% HF dip/ spin dry, which resulted in a H-terminated surface. The H was removed at 550 °C in vacuum prior to rowth. The growth of the B-doped SiGe layer was done at 350 °C to minimize segregation and diffusion of the Ge and B. Doping levels of 2×1020/cm3 were obtained with near 100% activation. Using Si0.35, doped with 2×1020 B/cm3, a cut-off wavelength of 11.1 μm and an emission coefficient of 19.8 %/eV were obtained for discrete detectors. Preliminary results from the detector arrays show full functionality in the spectral range of 6.1 to 12.8 μm.


1993 ◽  
Vol 298 ◽  
Author(s):  
C. Peng ◽  
L. Tsybeskov ◽  
P.M. Fauchet ◽  
F. Seiferth ◽  
S.K. Kurinec ◽  
...  

AbstractWe have investigated the properties of light-emitting porous silicon (LEpSi) after standard microelectronic processing steps such as annealing, thermal and chemical oxidation, ion implantation, and reactive ion etching. The nature of the physical and chemical changes induced by these processing steps is studied. After thermal or chemical oxidation, the photoluminescence (PL) from LEpSi is blue shifted and more stable. Low dose dopant implantation essentially keeps the PL spectrum unchanged. Thermal annealing after ion implantation affects the PL intensity differently, depending on the type of ions. Reactive ion etching changes the surface morphology and shifts the PL peak to blue.


2000 ◽  
Vol 638 ◽  
Author(s):  
Christopher C. Striemer ◽  
Philippe M. Fauchet ◽  
Leonid Tsybeskov

AbstractTwo-dimensional periodic arrays of inverted pyramid holes with nanometer scale have been patterned on the surface of a (100) silicon wafer and studied for possible application in nanoscale silicon based devices. The surface patterning employed a simple microelectronic processing scheme in which the standing wave intensity pattern from two interfering 458nm laser beams was used to expose holes in a photoresist layer. Subsequent dry etching through an underlying oxide mask layer, followed by a KOH etching step yielded a highly periodic, large area array of inverted pyramids. The pyramid geometry is formed during the anisotropic KOH etch, which stops at the (111) pyramid walls. Therefore, the tips of all inverted pyramids are formed by the intersection of (111) silicon crystal planes and have identical geometry. This study focuses on the use of these features as templates for the controlled crystallization of amorphous silicon layers and also as electric field concentrating “funnels” in MOS-type structures. We will discuss a proposed device in which silicon nanocrystals will be incorporated into the concentrated electric field region at the tip of each inverted pyramid. With this structure, the charging of identical addressable nanocrystals may be possible, leading to the development of practical nanoscale silicon devices.


1991 ◽  
Author(s):  
Meyya Meyyappan ◽  
T. R. Govindan ◽  
John P. Kreskovsky

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