TCAD simulation study on reliability issue of heterojunction heterodielectric FinFET: Effect of interface trap charge, BOX height and temperature

Pramana ◽  
2021 ◽  
Vol 95 (4) ◽  
Author(s):  
Yash Hirpara ◽  
Rajesh Saha
2012 ◽  
Vol 717-720 ◽  
pp. 1101-1104 ◽  
Author(s):  
M.G. Jaikumar ◽  
Shreepad Karmalkar

4H-Silicon Carbide VDMOSFET is simulated using the Sentaurus TCAD package of Synopsys. The simulator is calibrated against measured data for a wide range of bias conditions and temperature. Material parameters of 4H-SiC are taken from literature and used in the available silicon models of the simulator. The empirical parameters are adjusted to get a good fit between the simulated curves and measured data. The simulation incorporates the bias and temperature dependence of important physical mechanisms like interface trap density, coulombic interface trap scattering, surface roughness scattering and velocity saturation.


2009 ◽  
Vol 518 (5) ◽  
pp. 1595-1598 ◽  
Author(s):  
Shu-Tong Chang ◽  
Wei-Ching Wang ◽  
Chang-Chun Lee ◽  
Jacky Huang

2021 ◽  
Vol 21 (8) ◽  
pp. 4252-4257
Author(s):  
Tae Jun Ahn ◽  
Yun Seop Yu

We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.


2019 ◽  
Vol 103 ◽  
pp. 104605
Author(s):  
H. Bijo Joseph ◽  
Sankalp Kumar Singh ◽  
R.M. Hariharan ◽  
Yusuf Tarauni ◽  
D. John Thiruvadigal

2004 ◽  
Vol 1 (18) ◽  
pp. 556-561
Author(s):  
Akihiro Uehara ◽  
Keiichiro Kagawa ◽  
Takashi Tokuda ◽  
Jun Ohta ◽  
Masahiro Nunoshita

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