Impact of Interface Trap Charge on Analog/RF parameters of Novel Heterogeneous Gate Dielectric Tri-Metal Gate FinFET

2021 ◽  
Author(s):  
Somya Saraswat ◽  
Dharmendra Singh Yadav
Keyword(s):  
Gate Dielectric ◽  
Interface Trap ◽  
Metal Gate ◽  
Trap Charge

Impact of interface trap charges on Junctionless double and triple metal gate High-k Gate All Around Nanowire FET based Alzheimer Biosensor

2021 ◽  
Author(s):  
Rishu Chaujar ◽  
Mekonnen Getnet Yirak
Keyword(s):  
Threshold Voltage ◽  
Positive Impact ◽  
Drain Current ◽  
Interface Trap ◽  
Metal Gate ◽  
High K ◽  
Current Threshold ◽  
Subthreshold Voltage ◽  
Output Characteristics ◽  
The Impact

Abstract In this work, junctionless double and triple metal gate high-k gate all around nanowire field-effect transistor-based APTES biosensor has been developed to study the impact of ITCs on device sensitivity. The analytical results were authenticated using ‘‘ATLAS-3D’’ device simulation tool. Effect of different interface trap charge on the output characteristics of double and triple metal gate high-k gate all around junctionless NWFET biosensor was studied. Output characteristics, like transconductance, output conductance,drain current, threshold voltage, subthreshold voltage and switching ratio, including APTES biomolecule, have been studied in both devices. 184% improvement has been investigated in shifting threshold voltage in a triple metal gate compared to a double metal gate when APTES biomolecule immobilizes on the nanogap cavity region under negative ITCs. Based on this finding, drain off-current ratio and shifting threshold voltage were considered as sensing metrics when APTES biomolecule immobilizes in the nanogap cavity under negative ITCs which is significant for Alzheimer's disease detection. We signifies a negative ITC has a positive impact on our proposed biosensor device compared to positive and neutral ITCs.

Dual Work Function CMOS Gate Technology Based on Metal Interdiffusion

2001 ◽  
Vol 670 ◽  
Author(s):  
Igor Polishchuk ◽  
Pushkar Ranade ◽  
Tsu-Jae King ◽  
Chenming Hu
Keyword(s):  
Gate Dielectric ◽  
New Technology ◽  
Cmos Technology ◽  
Dielectric Surface ◽  
Metal Gate ◽  
Gate Electrodes ◽  
Mos Devices ◽  
Low Threshold ◽  
Work Functions ◽  
Electrical Reliability

ABSTRACTIn this paper we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve a low threshold voltage for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not compromise the integrity and electrical reliability of the gate dielectric. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.

Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter

2021 ◽  
Vol 21 (8) ◽  
pp. 4252-4257
Author(s):  
Tae Jun Ahn ◽  
Yun Seop Yu
Keyword(s):  
Computer Aided Design ◽  
Field Effect Transistors ◽  
Three Dimensional ◽  
Interface Trap ◽  
Charge Effects ◽  
Trap Charge ◽  
Interlayer Dielectric ◽  
Threshold Voltages ◽  
Propagation Delays ◽  
Aided Design

We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.

scholarly journals A high-sensitive digital photosensor using MOS interface-trap charge pumping

2004 ◽  
Vol 1 (18) ◽  
pp. 556-561
Author(s):  
Akihiro Uehara ◽  
Keiichiro Kagawa ◽  
Takashi Tokuda ◽  
Jun Ohta ◽  
Masahiro Nunoshita
Keyword(s):  
Interface Trap ◽  
Trap Charge ◽  
Charge Pumping

Chemical Stability of Advanced Metal Gate and Ultra-thin Gate Dielectric Interface During Rapid Thermal Annealing

1998 ◽  
Vol 525 ◽  
Author(s):  
B. Claflin ◽  
M. Binger ◽  
G. Lucovsky
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Chemical Stability ◽  
Electron Spectroscopy ◽  
Auger Electron ◽  
Elevated Temperatures ◽  
Gate Dielectric ◽  
Metal Gate ◽  
Dielectric Interface ◽  
On Line

ABSTRACTThe chemical stability of the compound metals TiNx and WNx on SiO2 and SiO2/Si3N4 (ON) dielectric stacks is studied by on-line Auger electron spectroscopy (AES) following sequential rapid thermal annealing treatments of 15 - 180 s up to 850 °C. The TiNx/SiO2 interface reacts at 850 °C and the reaction is kinetics driven. The TiNx/Si3N4 interface is more stable than TiNx/SiO2 even after a 180 s anneal at 850 °C. WNx is stable below 650 °C both on SiO2 and Si3N4, but above this temperature the film changes, possibly due to crystallization or interdiffusion. The changes in the WNx film are not controlled by kinetics. The compound metals are chemically more stable at elevated temperatures than pure Ti or W on SiO2.

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