A methodology for designing cutting drum of surface miner to achieve production of desired chip size

Sadhana ◽  
2020 ◽  
Vol 45 (1) ◽  
Author(s):  
A Prakash ◽  
V M S R Murthy ◽  
K B Singh ◽  
C Kumar ◽  
L A Kumaraswamidhas
Keyword(s):  
Surface Miner ◽  
Chip Size

Development of Wafer Level Chip Size Packaging Process and its Application to the CMOS Image Sensor Module for Medical Device

2017 ◽  
Vol 137 (2) ◽  
pp. 48-58
Author(s):  
Noriyuki Fujimori ◽  
Takatoshi Igarashi ◽  
Takahiro Shimohata ◽  
Takuro Suyama ◽  
Kazuhiro Yoshida ◽  
...  
Keyword(s):  
Medical Device ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Wafer Level ◽  
Packaging Process ◽  
Sensor Module ◽  
Chip Size

scholarly journals Effects of microwave irradiation on the moisture content of various wood chip fractions obtained from different tree species

2021 ◽  
Vol 67 (1) ◽  
Author(s):  
Monika Aniszewska ◽  
Krzysztof Słowiński ◽  
Ewa Tulska ◽  
Witold Zychowicz
Keyword(s):  
Moisture Content ◽  
Microwave Irradiation ◽  
Microwave Power ◽  
Irradiation Time ◽  
Initial Moisture Content ◽  
Radiant Energy ◽  
Wood Chip ◽  
Wood Chips ◽  
Chip Size ◽  
Drying Rates

AbstractThe paper proposes the use of microwave irradiation to lower the initial moisture content of wood chips. The study involved willow and fir chips fractionated by means of a sieve separator and unfractionated ash chips. The wood chips were exposed to a constant microwave power of 800 W for 30 s, 60 s, 120 s and 180 s. The chips were weighed before and after irradiation to measure loss of moisture. It was found that the decline in moisture content increased with wood chip size for a given irradiation time and microwave power. The initial moisture content of wood chips was not found to significantly affect loss of moisture as the drying rates of wood chips with higher and lower moisture content exposed to microwaves were not statistically different. The results showed that irradiation intensity increased with the time of exposure to microwaves and unit radiant energy per unit of evaporated moisture decreased with increasing wood chip size in the 3.15–31.50 mm range.

Current and Future Three-Dimensional LSI Integration Technology by “chip on chip”, “chip on wafer” and “wafer on wafer”

2006 ◽  
Vol 970 ◽  
Author(s):  
Manabu Bonkohara ◽  
Makoto Motoyoshi ◽  
Kazutoshi Kamibayashi ◽  
Mitsumasa Koyanagi
Keyword(s):  
Three Dimensional ◽  
Process Time ◽  
Future Technology ◽  
Sensor Device ◽  
Research Level ◽  
Key Technologies ◽  
The Future ◽  
Chip Size ◽  
On Chip ◽  
Chip Chip

ABSTRACTRecently the development of three dimensional LSI (3D-LSI) has been accelerated and its stage has changed from the research level or limited production level to the investigation level with a view to mass production. This paper describes the current and the future 3D-LSI technologies which we have considered and imagined. The current technology is taken our Chip Size Package (CSP) for sensor device, for instance. In the future technology, there are the five key technologies are described. And considering con and pro of the current 3D LSI stacked approach, such as CoC (Chip on Chip), CoW (Chip on Wafer) and WoW (Wafer on Wafer), We confirmed that CoW combined with Super-Smart-Stack (SSS™) technology will shorten the process time per chip at the same level as WoW approach and is effective to minimize process cost.

Ultrathin wafer level chip size package

2000 ◽  
Vol 23 (2) ◽  
pp. 212-214 ◽  
Author(s):  
A. Badihi
Keyword(s):  
Wafer Level ◽  
Chip Size

Effect of Aggregate Size on the Retention of Conventional and Rubberized Chip Seal

2019 ◽  
Author(s):  
Alireza Pourhassan ◽  
Ahmed A. Gheni ◽  
Mohamed A. ElGawady
Keyword(s):  
Impact Load ◽  
Mechanical Energy ◽  
Aggregate Size ◽  
Crumb Rubber ◽  
Superior Performance ◽  
Natural Aggregate ◽  
Modes Of Failure ◽  
Chip Seal ◽  
Chip Size ◽  
On Chip

<p>A common defect of chip seals is chip loss or raveling. The previous studies showed uniform grading of aggregate will enhance the retention ability of the chip seal. Also, it was shown that using crumb rubber as an aggregate will enhance the chip seal behavior including aggregate retention. However, no specific study has been done focusing on the effect of aggregate size for rubber nor natural aggregate. This paper is evaluating the effect of chip size on aggregate retention of both natural and rubber aggregate. Standard and modified Vialit tests, and standard and modified Pennsylvania tests which apply different forms of mechanical energy in different temperature was used to assess the aggregate-binder bond interaction and study the chip seal retention. Test results showed different trends for the effect of size on chip retention under impact load versus dynamic load because of different modes of failure. However, rubber particles showed a superior performance rather than natural aggregate in all cases.</p>

scholarly journals A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

2017 ◽  
Vol 7 (1.3) ◽  
pp. 69
Author(s):  
M. Ramana Reddy ◽  
N.S Murthy Sharma ◽  
P. Chandra Sekhar
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Power Consumption ◽  
Common Gate ◽  
Chip Size ◽  
Overall Performance ◽  
Amplifier Design ◽  
Noise Amplifier

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

Discrete Element Simulation of the Stress Wave in High Speed Milling

2017 ◽  
Author(s):  
Yifei Jiang ◽  
Jun Zhang ◽  
Yong He ◽  
Hongguang Liu ◽  
Afaque Rafique Memon ◽  
...  
Keyword(s):  
High Speed ◽  
Cutting Tool ◽  
Cutting Speed ◽  
Discrete Element ◽  
Rake Angle ◽  
Stress Waves ◽  
High Speed Milling ◽  
Element Simulation ◽  
Chip Size ◽  
Distribution Of Stress

As cutting tool penetrates into workpiece, stress waves is induced and propagates in the workpiece. This paper aims to propose a two-dimensional discrete element method to analyze the stress waves effects during high speed milling. The dependence of the stress waves propagation characteristics on rake angle and cutting speed was studied. The simulation results show that the energy distribution of stress waves is more concentrated near the tool tip as the rake angle or the cutting speed increases. In addition, the density of initial cracks in the workpiece near the cutting tool increases when the cutting speed is higher. The high speed milling experiments indicate that the chip size decreases as the cutting speed increases, which is just qualitatively consistent with the simulation.

Design of Broadband LNA Using Improved Self-Bias Architecture

2019 ◽  
Vol 28 (08) ◽  
pp. 1920005 ◽  
Author(s):  
Tian Qi ◽  
Songbai He
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Power Gain ◽  
Matching Networks ◽  
Self Bias ◽  
Measurement Results ◽  
Chip Size ◽  
Simulation Results ◽  
Noise Amplifier ◽  
Ku Band

A broadband low-noise amplifier (LNA) using 0.13 [Formula: see text]m GaAs HEMT technology for Ku-band applications is presented in this paper. By introducing an improved self-bias architecture, the LNA is achieved with low noise figure (NF) and high power gain. Compared with traditional LNA, self-bias architecture can reduce DC supplies to single one, and the improved architecture proposed here also takes part in source matching to reduce the complexity matching networks for broadband applications. To verify, an LNA operating over 12–18-GHz bandwidth is fabricated. The measurement results, for all the 72 chips on the wafer, and their average values are in great accordance with the simulation results, with 25.5–27.5-dB power gain, 1.1–1.8-dB NF, 15–17.5-dBm output power at [Formula: see text] and with a chip size of 2 mm [Formula: see text] 1.5 mm.

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