Effect of Aggregate Size on the Retention of Conventional and Rubberized Chip Seal

2019 ◽  
Author(s):  
Alireza Pourhassan ◽  
Ahmed A. Gheni ◽  
Mohamed A. ElGawady
Keyword(s):  
Impact Load ◽  
Mechanical Energy ◽  
Aggregate Size ◽  
Crumb Rubber ◽  
Superior Performance ◽  
Natural Aggregate ◽  
Modes Of Failure ◽  
Chip Seal ◽  
Chip Size ◽  
On Chip

<p>A common defect of chip seals is chip loss or raveling. The previous studies showed uniform grading of aggregate will enhance the retention ability of the chip seal. Also, it was shown that using crumb rubber as an aggregate will enhance the chip seal behavior including aggregate retention. However, no specific study has been done focusing on the effect of aggregate size for rubber nor natural aggregate. This paper is evaluating the effect of chip size on aggregate retention of both natural and rubber aggregate. Standard and modified Vialit tests, and standard and modified Pennsylvania tests which apply different forms of mechanical energy in different temperature was used to assess the aggregate-binder bond interaction and study the chip seal retention. Test results showed different trends for the effect of size on chip retention under impact load versus dynamic load because of different modes of failure. However, rubber particles showed a superior performance rather than natural aggregate in all cases.</p>

Water Film Depth Prediction Model for Highly Textured Pavement Surface Drainage

2021 ◽  
pp. 036119812110363
Author(s):  
Alireza Pourhassan ◽  
Ahmed A. Gheni ◽  
Mohamed A. ElGawady
Keyword(s):  
Prediction Model ◽  
Water Film ◽  
Crumb Rubber ◽  
Surface Material ◽  
Textured Surfaces ◽  
Road Traffic Safety ◽  
Material Type ◽  
Chip Seal ◽  
On Chip ◽  
Effect Of Surface

Water film depth (WFD) is an important factor for road traffic safety because of its direct connection with skid resistance, hydroplaning speed, and the tendency of splash and spray. Increasing the pavement macrotexture reduces WFD. However, existing models for WFD prediction have not been developed on highly textured surfaces such as chip seal. Furthermore, the rainfall intensities used for developing most of these models were relatively low, leaving no or low WFD on chip seal surfaces. To propose a WFD prediction model suitable for highly textured surfaces and to consider the effect of surface material type, an experimental study was conducted with 154 different combinations of mean texture depth (MTD), surface material type, surface slope, drainage length, and rainfall intensity. The tests were carried out on chip seal specimens using a full-scale rainfall simulator. Test results from 1,784 WFD readings indicated that the Gallaway and PAVDRN models were not accurate for highly textured surfaces used in this study with MTD ranging from 0.05 to 0.20 in. Two experimental models were, therefore, proposed to predict the WFD; both models displayed a significantly higher correlation between the measured and predicted WFD compared with the existing models. Furthermore, the eco-friendly rubberized chip seal showed an enhanced drainage capability compared with conventional chip seal, especially in low slopes, because of the hydrophobic nature of crumb rubber versus the hydrophilic character of mineral aggregates. Accordingly, the proposed model incorporated a term to consider the effect of surface material type.

Leaching Assessment of Eco-Friendly Rubberized Chip Seal Pavement

2018 ◽  
Vol 2672 (52) ◽  
pp. 67-77 ◽  
Author(s):  
Ahmed Gheni ◽  
Xuesong Liu ◽  
Mohamed A. ElGawady ◽  
Honglan Shi ◽  
Jianmin Wang
Keyword(s):  
Ph Value ◽  
The United States ◽  
Crumb Rubber ◽  
Recycled Aggregate ◽  
Metal Leaching ◽  
Toxic Heavy Metals ◽  
Asphalt Emulsion ◽  
Natural Aggregate ◽  
Chip Seal ◽  
Ph Conditions

Companies in the United States need to mine billions of tons of raw natural aggregate each year. At the same time, billions of scrap tires are stockpiled every year. As a result, replacing the natural aggregate with recycled aggregate is beneficial to the construction industry and the environment. This paper is part of a comprehensive project that developed, and field implemented, a new eco-friendly rubberized chip seal where the mineral aggregate in chip seal is partially or totally replaced with crumb rubber made of recycled tires. This paper presents an extensive study of the environmental impact of using rubber aggregate in chip seal pavement in terms of leaching under different pH conditions, including simulated acid rain. The results are compared with those of conventional chip seal. Leaching from the constituents of chip seal, that is, rubber aggregate and emulsion, was investigated. Two types of rubber and two types of asphalt emulsions were studied. The leaching performance of rubberized chip seal was also investigated. This study revealed that the toxic heavy metals leached from the rubberized chip seal, for pH ranging from 4 to 10, were below that of the EPA drinking water standards. In addition, a significant reduction of heavy metal leaching was recorded when rubber was used with emulsion in the form of chip seal pavement under different pH conditions. Finally, the metal leaching in all types of samples (including rubber, asphalt emulsion, and chip seal) decreased with the increase in pH value.

Current and Future Three-Dimensional LSI Integration Technology by “chip on chip”, “chip on wafer” and “wafer on wafer”

2006 ◽  
Vol 970 ◽  
Author(s):  
Manabu Bonkohara ◽  
Makoto Motoyoshi ◽  
Kazutoshi Kamibayashi ◽  
Mitsumasa Koyanagi
Keyword(s):  
Three Dimensional ◽  
Process Time ◽  
Future Technology ◽  
Sensor Device ◽  
Research Level ◽  
Key Technologies ◽  
The Future ◽  
Chip Size ◽  
On Chip ◽  
Chip Chip

ABSTRACTRecently the development of three dimensional LSI (3D-LSI) has been accelerated and its stage has changed from the research level or limited production level to the investigation level with a view to mass production. This paper describes the current and the future 3D-LSI technologies which we have considered and imagined. The current technology is taken our Chip Size Package (CSP) for sensor device, for instance. In the future technology, there are the five key technologies are described. And considering con and pro of the current 3D LSI stacked approach, such as CoC (Chip on Chip), CoW (Chip on Wafer) and WoW (Wafer on Wafer), We confirmed that CoW combined with Super-Smart-Stack (SSS™) technology will shorten the process time per chip at the same level as WoW approach and is effective to minimize process cost.

Failure Modes of Tapered Suction Caissons Under Vertical Pull-Out Loads

2007 ◽  
Author(s):  
Mahmood Nabipour ◽  
Mostafa Zeinoddini ◽  
Mahmood R. Abdi
Keyword(s):  
Failure Modes ◽  
Numerical Approach ◽  
Local Failure ◽  
Superior Performance ◽  
Soil Plug ◽  
Pull Out ◽  
Modes Of Failure ◽  
Numerical Studies ◽  
Second Mode ◽  
Suction Caissons

The pull-out performance of conventional upright suction caissons has been investigated by different researchers. However, no attention has been formerly paid to tapered suction caissons. Some numerical studies already conducted by the authors demonstrated that tapered caissons exhibit pull-out capacities well above than that from their corresponding upright caissons. This paper deals with different failure mechanisms of tapered suction caissons and discusses some reason for their superior performance. A numerical approach has been used and different combinations of caisson types/ soil categories have been examined. With tapered suction caissons two different modes of failure have been discerned. The first mode has been noticed to develop in weak clays and sands under drained conditions. This mode corresponds to a shear sliding failure in the soil plug along the caisson’s interior wall. Concurrently a soil wedge is formed in the soil body adjacent to the caisson. The second mode of failure has been observed in higher strength drained clays and undrained clays and sands. With this failure mode a local failure at the bottom of the soil plug has been noticed to happen. At the same time the failure is extended to the lower surfaces of a soil wedge outside of the caisson. The detached soil plug accompanies the caisson in its movement upward following the local failure.

A Complete Stochastic Wiring Distribution for Gigascale Integration (GSI)

1996 ◽  
Vol 427 ◽  
Author(s):  
Jeffrey A. Davis ◽  
John C. Eble ◽  
Vivek K. De ◽  
James D. Meindl
Keyword(s):  
Empirical Relationship ◽  
Length Distribution ◽  
Gigascale Integration ◽  
Low Dielectric ◽  
Chip Size ◽  
Overall Performance ◽  
Copper Aluminum ◽  
On Chip ◽  
Generic System ◽  
New Distribution

AbstractBased on Rent's Rule, a well established empirical relationship, a rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed. The distribution is then used to describe an optimal architecture for a multilevel wiring network that provides maximum interconnect density and minimum chip size for a ULSI system. In addition, this new distribution has been incorporated into a Generic System Simulator (GENESYS), that projects overall performance of future ULSI systems. Assuming various interconnect materials such as copper, aluminum, silicon dioxide, and low dielectric polymers, GENESYS has been used to examine the effects that each material has on overall performance of ASIC's over the next 15 years.

Evaluation of a Line Laser Scanner to Improve the Measurement of Average Least Dimension in Chip Seal Design Methods

2018 ◽  
Vol 2672 (40) ◽  
pp. 59-67
Author(s):  
Sareh Kouchaki ◽  
Hossein Roshani ◽  
Jorge A. Prozzi ◽  
Cristina Cordoba ◽  
Joaquin Bernardo Hernandez
Keyword(s):  
High Speed ◽  
Laser Scanner ◽  
Preventive Treatment ◽  
Structural Condition ◽  
Application Rate ◽  
Seal Design ◽  
Chip Seal ◽  
Highly Correlated ◽  
On Chip ◽  
Aggregate Particles

Chip seal, as the most widespread pavement preventive treatment, is regularly applied on existing pavements that are still in good structural condition to increase the pavement serviceability. The most effective key parameter on chip seal performance is binder application rate, which directly governs chip seal distresses such as bleeding and raveling. How this rate is calculated mainly depends on the value of least dimension (LD) of aggregate particles. However, the available measuring methods of LD value are slow, laborious, and subjective. This study presents the development of a new high-speed line laser scanner (LLS) prototype to measure the LD value of particles more quickly and accurately. The LD values of aggregate particles were also measured using a digital caliper and considered as control data. The repeatability and reliability of the developed LLS prototype were evaluated, as well as the speed of the prototype in calculating the LD values of 100 aggregate particles. The findings indicate that the measurements of the developed prototype are highly correlated with those of the caliper. In addition, it was found that the developed prototype is efficient and capable of calculating the LD values of several particles simultaneously.

Thermo-Viscoelastic Analysis for Warpage in CSP With Different Viscoelastic Properties for Several Layers

2007 ◽  
Author(s):  
Hideo Koguchi ◽  
Atsushi Ueno
Keyword(s):  
Thermal Expansion ◽  
Theoretical Analysis ◽  
Manufacturing Process ◽  
Viscoelastic Properties ◽  
Layered Material ◽  
Viscoelastic Analysis ◽  
Chip Size ◽  
The Difference ◽  
On Chip ◽  
Layered Body

In this study, a simple theory for estimating the warpage of chip size packaging (CSP) during a manufacturing process is presented. A single-sided CSP which is composed of IC, a resin and a substrate is modeled for an analysis as a three-layered material. Especially, the resin and the substrate have different thermo-viscoelastic properties. When the layered body is perfectly bonded, its warpage is caused by the difference of the thermal expansion coefficient in each layer when temperature varies. The warpage of CSP for a various thicknesses of the IC and the substrate is investigated. Finally, the warpage calculated using the theory is compared with the result in experiment, and both results are well agreed with each other. Then, it is shown that the simple theoretical analysis is valid. After that, this program is extended to be able to analyze the warpage in a CoC (Chip on Chip), and the result of the analysis is then presented.

scholarly journals A Sub-THz Wireless Power Transfer for Non-Contact Wafer-Level Testing

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1210
Author(s):  
Hanh Dang-ba ◽  
Gyung-su Byun
Keyword(s):  
Wireless Power Transfer ◽  
Cmos Technology ◽  
Power Delivery ◽  
Transfer Efficiency ◽  
Power Transfer ◽  
Wireless Power ◽  
Wafer Level ◽  
Power Transfer Efficiency ◽  
Chip Size ◽  
On Chip

In this paper, a sub-THz wireless power transfer (WPT) interface for non-contact wafer-level testing is proposed. The on-chip sub-THz couplers, which have been designed and analyzed with 3-D EM simulations, could be integrated into the WPT to transfer power through an air media. By using the sub-THz coils, the WPT occupies an extremely small chip size, which is suitable for future wafer-testing applications. In the best power transfer efficiency (PTE) condition of the WPT, the maximum power delivery is limited to 2.5 mW per channel. However, multi-channel sub-THz WPT could be a good solution to provide enough power for testing purposes while remaining high PTE. Simulated on a standard 28-nm CMOS technology, the proposed eight-channel WPT could provide 20 mW power with the PTE of 16%. The layouts of the eight-channel WPT transmitter and receiver occupy only 0.12 mm2, 0.098 mm2, respectively.

Design and Calibration of MIMU Based on Chip Size Micro Inertial Sensors

2013 ◽  
Vol 849 ◽  
pp. 302-309
Author(s):  
Yun Xu ◽  
Xin Hua Zhu ◽  
Yu Wang
Keyword(s):  
High Performance ◽  
Inertial Sensors ◽  
Low Cost ◽  
Rapid Development ◽  
Experimental Result ◽  
Integrated Navigation ◽  
Bias Stability ◽  
Chip Size ◽  
Order Of Magnitude ◽  
On Chip

With rapid development of micro fabrication technology, the performance of MIMU has gradually improved. The MIMU introduced in this paper is based on the silicon micro machined gyroscope of type MSG7000D and accelerometer of type MSA6000. The volume of it is 3×3×3cm3, the mass is 68.5g and the power consumption is less than 1w. The experimental result shows that the bias stability of the gyroscope and accelerometer for each axis of the designed MIMU is less than 10°/h and 0.5mg respectively. For the non orthogonality in three axes of the structure, MIMU needs to be calibrated. After calibration, the measurement accuracy has improved by an order of magnitude. The designed MIMU can satisfy the requirement of high performance, low cost, light weight and small size for strap-down navigation system, thus it can be widely applied not only to the field of vehicles integrated navigation, attitude measurement but also to the fields of personal goods such as mobile, game consoles and so on.

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