Linearity and Analog Performance Analysis of Silicon Junctionless Bulk FinFET Considering Gate Electrode Workfunction Variability and Different Fin Aspect Ratio

Silicon ◽  
2021 ◽  
Author(s):  
Kalyan Biswas ◽  
Angsuman Sarkar ◽  
Chandan Kumar Sarkar
2011 ◽  
Vol 6 (2) ◽  
pp. 102-106
Author(s):  
Milene Galeti ◽  
Michele Rodrigues ◽  
Nadine Collaert ◽  
Eddy Simoen ◽  
Cor Claeys ◽  
...  

This work presents an analysis of the analog performance of SOI MuGFET devices and the impact of different TiN metal gate electrode thickness.Thinner TiN metal gate allows achieving large gain and this effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. This VEA increase suggests an increase of the transversal electrical field for thin TiN metal gate (reduced gate oxide thickness) that is confirmed with the increment of the GIDL current.This impact on the voltage gain is maintained for short channel length.The impact of different gate dielectrics was also studied where high-k dielectric indicated a higher VT due to a VFB variation. Additionally, lower intrinsic voltage gain was observed for hafnium dielectric and this can be related to the lower Early voltage (VEA) present in this devices.


Author(s):  
Dae-Hwan Lee ◽  
Ki-Ju Baek ◽  
Ji-Hoon Ha ◽  
Kee-Yeol Na ◽  
Yeong-Seuk Kim

2021 ◽  
Author(s):  
Neeraj Jain ◽  
Kunal Singh ◽  
Shashi Kant Sharma ◽  
Renu Kumawat

Abstract This work reports RF and analog performance analysis of an amorphous Indium Tin Zinc Oxide thin film transistor. The various parameters affecting the performance of a-ITZO TFT like drain current, drain conductance, output resistance, transconductance, transconductance generation factor, early voltage, intrinsic gain, capacitances, cut off frequency, maximum frequency of oscillation, transconductance frequency product, gain frequency product, gain bandwidth product and gain transconductance frequency product have been closely examined. The device is further analyzed to investigate the impact of variation in physical parameters viz. dielectric material, dielectric thickness (𝐷𝑡 ) and temperature (T) on the RF/Analog performance. Use of high-k dielectric material in the simulated structure has resulted in low subthreshold slope (SS) of 0.62 V/decade, On voltage (𝑉𝑜𝑛) of (- 0.29) V, 𝐼𝑜𝑛/𝐼𝑜𝑓𝑓 ratio of ~ 109 , intrinsic gain (𝐴𝑉) of 104.5 dB and gain frequency product (GFP) of 1.86 GHz. The best results for dielectric thickness variation are offered for dielectric thickness of 150 nm with SS of 0.22 V/decade, 𝑉𝑜𝑛 of (-0.26 V), 𝐼𝑜𝑛/𝐼𝑜𝑓𝑓 of ~ 1010 , (𝐴𝑉) of 175.69 dB and GFP of 2.39 GHz. For device reliability and stability study, temperature analysis has also been done. To demonstrate the circuit level implementation of the simulated structure, a resistive load inverter circuit is simulated and analyzed for different variations (high-k, 𝐷𝑡 and T). The results obtained are promising to meet the current display industry requirement. It has also been concluded that TFT with high-k material or thinner dielectric at T=300 K provides best performance.


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