scholarly journals Analog Performance of SOI nMuGFETs with Different TiN Gate Electrode Thickness and High-k Dielectrics

2011 ◽  
Vol 6 (2) ◽  
pp. 102-106
Author(s):  
Milene Galeti ◽  
Michele Rodrigues ◽  
Nadine Collaert ◽  
Eddy Simoen ◽  
Cor Claeys ◽  
...  
Keyword(s):  
Oxide Thickness ◽  
Voltage Gain ◽  
Gate Electrode ◽  
Metal Gate ◽  
Short Channel ◽  
High K ◽  
Analog Performance ◽  
Tin Metal ◽  
High K Dielectric ◽  
The Impact

This work presents an analysis of the analog performance of SOI MuGFET devices and the impact of different TiN metal gate electrode thickness.Thinner TiN metal gate allows achieving large gain and this effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. This VEA increase suggests an increase of the transversal electrical field for thin TiN metal gate (reduced gate oxide thickness) that is confirmed with the increment of the GIDL current.This impact on the voltage gain is maintained for short channel length.The impact of different gate dielectrics was also studied where high-k dielectric indicated a higher VT due to a VFB variation. Additionally, lower intrinsic voltage gain was observed for hafnium dielectric and this can be related to the lower Early voltage (VEA) present in this devices.

Impact of TiN/HfO2 Integration on Carrier Mobility

2006 ◽  
Vol 917 ◽  
Author(s):  
Mikael Casse ◽  
Laurent Thevenod ◽  
Bernard Guillaumot ◽  
Lucie Tosti ◽  
Vincent Cosnier ◽  
...  
Keyword(s):  
Experimental Data ◽  
Carrier Mobility ◽  
Interface Layer ◽  
Interface Roughness ◽  
Coulomb Scattering ◽  
Metal Gate ◽  
Coulombic Interactions ◽  
High K ◽  
High K Dielectric ◽  
The Impact

AbstractWe have investigated the impact of a metal gate (TiN) and high-k dielectric (HfO2) on the carrier mobility. We have shown that strong remote Coulomb scattering (RCS) due to charges in the HfO2 layer (either grown by ALD or MOCVD) mostly degrades the mobility at low/medium field. High amount of charges (>1013cm-2) is needed to explain the 30% degradation observed in devices with a thin interface layer. These additional coulombic interactions are effective for bottom oxide up to 2nm. We have developed a RCS model to fully explain the experimental data. The influence of the metal gate is also evidenced. The latter has a significative impact on the Si/SiO2 interface roughness, and may induce some additional coulombic interactions.

Effects of Film Stress Modulation Using TiN Metal Gate on Stress Engineering and Its Impact on Device Characteristics in Metal Gate/High-$k$ Dielectric SOI FinFETs

2008 ◽  
Vol 29 (5) ◽  
pp. 487-490 ◽  
Author(s):  
Chang Yong Kang ◽  
Ji-Woon Yang ◽  
Jungwoo Oh ◽  
Rino Choi ◽  
Young Jun Suh ◽  
...  
Keyword(s):  
Film Stress ◽  
Metal Gate ◽  
High K ◽  
Stress Engineering ◽  
Tin Metal ◽  
High K Dielectric

Effective Dielectric Thickness Scaling for High-K Gate Dielectric Mosfets

2002 ◽  
Vol 716 ◽  
Author(s):  
Krishna Kumar Bhuwalka ◽  
Nihar R. Mohapatra ◽  
Siva G. Narendra ◽  
V Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Channel Length ◽  
Short Channel ◽  
Dielectric Thickness ◽  
High K ◽  
Fringing Field ◽  
High K Dielectric ◽  
Physical Thickness

AbstractIt has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO2. In this work we have systematically evaluated the effective dielectric thickness for different Kgate to achieve targeted threshold voltage (Vt), drain-induced barrier lowering (DIBL) and Ion/Ioff ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO2 follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO2 is replaced by a high-K dielectric.

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

2009 ◽  
Vol 86 (3) ◽  
pp. 263-267 ◽  
Author(s):  
R. Gassilloud ◽  
F. Martin ◽  
C. Leroux ◽  
M. Hopstaken ◽  
X. Garros ◽  
...  
Keyword(s):  
Gate Electrode ◽  
Metal Gate ◽  
High K ◽  
High K Dielectric

SiGe channels for higher mobility CMOS devices

2009 ◽  
Vol 1194 ◽  
Author(s):  
Andreas Naumann ◽  
Torben Kelwing ◽  
Martin Trentzsch ◽  
Stephan Kronholz ◽  
Thorsten Kammler ◽  
...  
Keyword(s):  
Silicon Germanium ◽  
Chemical Vapor ◽  
Hole Mobility ◽  
Sige Layer ◽  
Cmos Process ◽  
Gate Electrode ◽  
Metal Gate ◽  
Gate Stack ◽  
Short Channel ◽  
High K

AbstractSilicon germanium (SiGe) is considered to substitute silicon (Si) as channel material of p-type MOSFET in future CMOS generations due to its higher hole mobility. In this work we investigate SiGe channels with a germanium concentration of 23 at% and 30 at%, even though the mobility is expected to be higher with even more germanium in the alloy. Low pressure chemical vapor deposition was used for SiGe deposition. A state of the art CMOS process including high-k dielectric and metal gate electrode was applied for fabrication of sub 50 nm gate length devices. As expected from the SiGe channel conduction and valence band offset the threshold voltage of the devices is influenced. The gate stack was directly deposited onto the SiGe layer consisting of a chemically grown base oxide, hafnium-based dielectric and titanium nitride gate electrode. C-V and I-V measurements show comparable CET and leakage values for the high-k metal gate stack on Si and SiGe channels. The trap density at the channel dielectric interface was determined using the charge pumping technique. The device characteristics of n- and p-MOSFETs with SiGe channels are compared to conventional Si channel devices. Short channel mobility was extracted with the gM,LIN-Method.

BJT effect analysis in p- and n-SOI MuGFETs with high-k gate dielectrics and TiN metal gate electrode for a 1T-DRAM application

2011 ◽  
Author(s):  
M. Galeti ◽  
M. Rodrigues ◽  
J. A. Martino ◽  
N. Collaert ◽  
E. Simoen ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Gate Electrode ◽  
Metal Gate ◽  
Effect Analysis ◽  
High K ◽  
Tin Metal

scholarly journals SOI n- and pMuGFET devices with different TiN metal gate thickness and crystallographic orientation of the sidewalls

2012 ◽  
Vol 7 (2) ◽  
pp. 107-112
Author(s):  
Michele Rodrigues ◽  
Milene Galeti ◽  
Nadine Collaert ◽  
Eddy Simoen ◽  
Cor Claeys ◽  
...  
Keyword(s):  
Crystallographic Orientation ◽  
Voltage Gain ◽  
Gate Electrode ◽  
Metal Gate ◽  
Electrode Thickness ◽  
Tin Metal ◽  
Output Conductance

This work presents an analysis of SOI p- and nMuGFET devices with different TiN metal gate electrode thickness for rotated and standard structures.Thinner TiN metal gate allows achieving a higher intrinsic voltage gain in spite of the reduced variation observed of the gm/IDS characteristics. This effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. Even with the larger mobility of the rotated nMuGFET devices when compared with the standard ones, the larger output conductance degradation resulted in an almost similar intrinsic voltage gain. P-channel devices, when implemented on the rotated layout, offer a lower intrinsic voltage gain.The GIDL current was also analyzed on these devices, indicating to be larger in thinner metal gate and rotated configuration.

Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high-k dielectric

2006 ◽  
Vol 83 (3) ◽  
pp. 460-462 ◽  
Author(s):  
Sang Ho Bae ◽  
Seung-Chul Song ◽  
KiSik Choi ◽  
Gennadi Bersuker ◽  
George A. Brown ◽  
...  
Keyword(s):  
Thickness Optimization ◽  
Metal Gate ◽  
Capping Layer ◽  
High K ◽  
Tin Metal ◽  
High K Dielectric
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