scholarly journals Time Amplifier Based Bang-Bang Phase Frequency Detector in 0.18μm CMOS Technology

2019 ◽  
Vol 9 (1S3) ◽  
pp. 85-89
Keyword(s):  
Dead Zone ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
Sense Amplifier ◽  
Time Amplifier ◽  
Frequency Detector ◽  
Cmos Implementation

A CMOS Implementation of Time amplifier (TA) based Bang-Bang Phase Frequency Detector (BBPFD) using Sense amplifier based flip flop (SAFF) is presented in this paper using 0.18μm CMOS technology. A time amplifier based on feedback output generator concept is utilized in minimizing the metastability and increasing the gain of TA which in turn boosts the gain of Phase Frequency Detector (PFD). Also, a modified SAFF was built in CMOS 0.18μm technology at 1.8V which further reduces the hysteresis and metastability aspect related to PFD. The proposed PFD works at a maximum frequency of 4GHz consuming 0.46mW of power with no dead zone.

PVT Aware Design of a Dead-zone Free High Speed Phase Frequency Detector in 90nm CMOS

2020 ◽  
Vol 13 (4) ◽  
pp. 516-530
Author(s):  
Suraj K. Saw ◽  
Madhusudan Maiti ◽  
Preetisudha Meher ◽  
Alak Majumder
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Speed ◽  
Dead Zone ◽  
Cmos Technology ◽  
Switching Noise ◽  
Phase Frequency Detector ◽  
Layout Area ◽  
Frequency Detector ◽  
Lock In

Background & Introduction: With the advent of technology, though the literature highlights many designs of Phase Frequency Detector (PFD), there remains some challenges like area overhead, switching noise near frequency lock point and fast, accurate response to mitigate dead zone and output errors. Methods: In this article, we have unearthed a low power, high speed and dead zone free PFD, which eliminates the switching noise near that lock-in node. This simple design uses lesser number of transistors to obtain smaller estimated layout area of 0.748mm2 and low power of 496.12μW, when operated at 10 GHz frequency at a power supply of 1.8V in 90nm CMOS technology. Results: The simulation reads a phase noise and output noise of -113.142dBc/Hz and -180.712dB at 1MHz offset. The circuit not only runs at a frequency as high as 40GHz, but also compatible to be operated at a power supply of as small as 0.9V. Conclusion: Process Variation analysis performed proves the robustness of the proposed circuit at all process corners. Also, the design gets validated at lower process nodes like 28nm UMC.

Phase-frequency detector in QCA nanotechnology using novel flip-flop with reset terminal

2020 ◽  
Vol 10 (2) ◽  
pp. 111-118
Author(s):  
Hani Alamdar ◽  
Gholamreza Ardeshir ◽  
Mohammad Gholami
Keyword(s):  
Flip Flop ◽  
Phase Frequency Detector ◽  
Frequency Detector

scholarly journals Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45 nm CMOS Technology

2021 ◽  
Vol 23 (11) ◽  
pp. 184-197
Author(s):  
Pawan Srivastava ◽  
◽  
Dr. Ram Chandra Singh Chauhan ◽  
Keyword(s):  
Frequency Synthesizer ◽  
Supply Voltage ◽  
Process Variations ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Monte Carlo Analysis ◽  
Voltage Controlled Oscillator ◽  
Phase Frequency Detector ◽  
Power Efficient ◽  
Frequency Detector

A novel phase frequency detector is designed which is made up of 16 transistors whereas conventional is of 48 transistors. This paper also presented the design of charge pump circuit and current starved VCO (CSVCO). These are the critical blocks that are widely used for applications like clock and data recovery circuit, PLL, frequency synthesizer. The proposed PFD eliminates the reset circuit using pass transistor logic and operates effectively at higher frequencies. The circuits are designed using Cadence Virtuoso v6.1 in 45nm CMOS technology having supply voltage 1V. It was found that the power consumption of PFD is 138.2 nW which is significantly lesser than other designs. CSVCO also analysed at operating frequency of 10 MHz to give output oscillation frequency of 1.119 GHz with power dissipation of 18.91 μW. Corner analysis done for both the PFD and CSVCO for various process variations. Monte Carlo analysis also done for the proposed PFD and presented CSVCO to test the circuit reliableness.

SINUSOIDAL CLOCKED SENSE-AMPLIFIER-BASED ENERGY RECOVERY FLIP-FLOPS

2014 ◽  
Vol 23 (05) ◽  
pp. 1450066
Author(s):  
JITENDRA KANUNGO ◽  
S. DASGUPTA
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Energy Recovery ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Sense Amplifier ◽  
Simulation Based ◽  
Digital Circuit Design

Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-amplifier based flip-flop (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed flip-flop operating with energy recovery single phase sinusoidal clock shows better performance. The proposed flip-flop also reduces the leakage current and glitch.

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