Design a Phase Frequency Detector

2013 ◽  
Vol 380-384 ◽  
pp. 3198-3203
Author(s):  
Xue Mei Lei ◽  
Xiao Dong Xing ◽  
Xue Dong Ding
Keyword(s):  
Power Consumption ◽  
Core Area ◽  
Operating Frequency ◽  
Cmos Process ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
High Frequencies ◽  
The Core ◽  
Input Signals ◽  
Frequency Detector

This paper describes a phase frequency detector application using 0.18μm CMOS process. In order to cover the high frequencies of input signals, TSPC D flip-flop structure are applied. The core area of proposal phase frequency detector is 60 μm×50 μm. The simulating results show that rang of operating frequency is from 500kHz to 500MHz and the power consumption is 0.722mW under a 1.8V supply.

scholarly journals Implementation of Phase Frequency Detector in Phase locked loop using Preset able modified TSPC D flip-flop

2019 ◽  
Vol 8 (12) ◽  
pp. 977-980
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Single Phase ◽  
Phase Locked Loop ◽  
Frequency Multiplier ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
Technology Applications ◽  
Phase Clock ◽  
Frequency Detector

Phase locked loop (PLL) forms an important part in many applications. Here design of PLL for frequency multiplier operation is considered. Frequency multiplier operation is implemented by using Preset able Modified Single Phase Clock (MTSPC) D flipflop logic circuits in Phase Frequency Detector (PFD). Preset able Modified Single Phase Clock (MTSPC) D flipflops functions at high speed with less power consumption. Noises in the form of glitches are introduced when a preset-able true single phase clocked D flipflop (TSPC) used in Phase Locked Loop. Preset-able modified TSPC (MTSPC) D flipflop used to overcome these glitches caused due to toggling at the output by use of PMOS. Technology applied is 90nm technology. Applications where better speed and reduced power consumption are required, this type of Phase locked loop (PLL) can be utilized.

Phase-frequency detector in QCA nanotechnology using novel flip-flop with reset terminal

2020 ◽  
Vol 10 (2) ◽  
pp. 111-118
Author(s):  
Hani Alamdar ◽  
Gholamreza Ardeshir ◽  
Mohammad Gholami
Keyword(s):  
Flip Flop ◽  
Phase Frequency Detector ◽  
Frequency Detector

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

AN ADC BASED RANDOM BIT GENERATOR BASED ON A DOUBLE SCROLL CHAOTIC CIRCUIT

2010 ◽  
Vol 19 (07) ◽  
pp. 1621-1639 ◽  
Author(s):  
VEDAT TAVAS ◽  
AHMET S. DEMIRKOL ◽  
SERDAR OZOGUZ ◽  
ALI ZEKI ◽  
ALI TOKER
Keyword(s):  
Power Consumption ◽  
Frequency Spectrum ◽  
Continuous Time ◽  
Binary Data ◽  
Test Suite ◽  
Cmos Process ◽  
Chaotic Circuit ◽  
Chip Area ◽  
The Core ◽  
Random Bit Generator

An A/D converter based random bit generator which exploits continuous-time chaos is presented. The chaotic circuit, which is used as the core of the random bit generator generates double-scroll attractor the frequency spectrum of which spans up to 80 MHz. The chaotic circuit was fabricated using a 0.35 μm CMOS process and the chip area, excluding pads, is 0.06 mm2. Power consumption of the integrated chip is 8 mW. Binary data obtained from the presented random bit generator pass the full NIST-800-22 test suite.

High Speed Min/Max Architecture Based on a Novel Comparator in 0.18-μm CMOS Process

2015 ◽  
Vol 24 (04) ◽  
pp. 1550048 ◽  
Author(s):  
Amir Fathi ◽  
Abdollah Khoei ◽  
Khayrollah Hadidi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Current Mode ◽  
Cmos Technology ◽  
Operating Frequency ◽  
Cmos Process ◽  
Fuzzy Logic Controllers ◽  
Speed Performance ◽  
External Clock ◽  
Frequency Feature

This paper describes the design of a high speed min/max architecture based on a new current comparator. The main advantage of the proposed circuit which employs a novel preamplifier-latch comparator is the higher operating frequency feature in comparison with previous works. Because the comparator can work in voltage mode, the min/max structure can be redesigned either in voltage or current mode. The designed comparator is refreshed without any external clock. Therefore, it does not degrade the speed performance of proposed min/max structure. These features along with low power consumption qualify the proposed architecture to be widely used in high speed fuzzy logic controllers (FLCs). Post-layout simulation results confirm 3.4 GS/s comparison rate with 9-bit resolution for a 0.9 V peak-to-peak input signal range for the comparator and 800 MHz operating frequency for min/max circuit. The power consumption of whole structure is 912 μW from a 1.8 V power supply using TSMC 0.18-μm CMOS technology.

scholarly journals Time Amplifier Based Bang-Bang Phase Frequency Detector in 0.18μm CMOS Technology

2019 ◽  
Vol 9 (1S3) ◽  
pp. 85-89
Keyword(s):  
Dead Zone ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
Sense Amplifier ◽  
Time Amplifier ◽  
Frequency Detector ◽  
Cmos Implementation

A CMOS Implementation of Time amplifier (TA) based Bang-Bang Phase Frequency Detector (BBPFD) using Sense amplifier based flip flop (SAFF) is presented in this paper using 0.18μm CMOS technology. A time amplifier based on feedback output generator concept is utilized in minimizing the metastability and increasing the gain of TA which in turn boosts the gain of Phase Frequency Detector (PFD). Also, a modified SAFF was built in CMOS 0.18μm technology at 1.8V which further reduces the hysteresis and metastability aspect related to PFD. The proposed PFD works at a maximum frequency of 4GHz consuming 0.46mW of power with no dead zone.

scholarly journals An integer-N frequency synthesizer for medical implantable devices

2021 ◽  
Author(s):  
Nima Haghighi
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Frequency Synthesizer ◽  
Wide Frequency Range ◽  
Implantable Devices ◽  
Total Power ◽  
Frequency Range ◽  
Phase Frequency Detector ◽  
Frequency Detector ◽  
Low Phase Noise

This thesis proposes an Integer-N frequency synthesizer in TSMC 0.18µm technology. The design is aimed for MICS (Medical Implantable Communication Services) devices operating at 402-406 MHz. A low phase noise, wide frequency range Quadrature Voltage Controlled Oscillator (QVCO) has been designed and simulated. The simulated phase noise @ 160 KHz offset is -100.3 dBc/Hz with the power consumption of 0.9 mW. This design addresses the small size, low phase noise and low power requirements for the Implantable devices. A wide frequency range Source Coupled Logic (SCL)32/33 prescaler divider has been designed. The program counter and Swallow counter have been implemented in Verilog-A which allow a division ratio of 2690 from the output of the QVCO. A phase frequency detector based on a modified TSPC D-Flip Flop is designed, which leads to a faster response time. The phase frequency detector, the charge pump, and the loop filter would consume 0.5 mW power. The total power consumption of the synthesizer is at 4.6 mW with 2% steady state settlement time of 160 μs.

A Novel Design of high performance low power phase frequency Detector for CMOS PLL frequency Synthesizer

2019 ◽  
Vol 09 ◽  
Author(s):  
Monika Bhardwaj ◽  
Sujata Pandey ◽  
Neeta Pandey
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Performance ◽  
Frequency Synthesizer ◽  
Operating Frequency ◽  
Feedback Signal ◽  
Input Frequency ◽  
Phase Frequency Detector ◽  
Pll Frequency Synthesizer ◽  
Frequency Detector

Aims: A high performance low power phase frequency detector is designed and simulated. The various different parameters of the circuit are obtained through various type of simulations. We worked mainly upon the power dissipation, power supply, input frequency range and its area. The proposed PFD will have the locking capability i.e. to lock at the edges either on the rising or falling edge w.r.t the reference and the feedback signal. The proposed design will have the very high performance and ultra-low phase noise. It has the added advantage of low cost and the compact size. Objective: The primary objective is to design a low power phase frequency detector for CMOS PLL Frequency Synthesizer using lows power technique. Method: The pass transistor logic is used in the circuit to eliminate the reset path. By this change of the path the operating frequency and operating speed both are increased in the proposed design. The input Frequency can be taken up to 5 gigahertz. The power supply is taken to be 1 V. The proposed PFD design will have a less number of transistors and also a low consumption of power. The output pulses of the PFD at phase difference of 0, 0,п/2, п, 3п/2, 2п will have its average voltage as 0, VDD and VDD/2. The proposed phase detector will perfectly detect the phase difference between two signals so that the harmonics problem can be minimized. Result: The proposed design is having its operating frequency as 5GHz over the conventional one which has its frequency as 800MHz. Power dissipation in the proposed design is reduced due to less number of transistors used as compared with the conventional one. The operating region has become much wider for proposed design as it is having operating frequency much higher than that of the conventional one. Conclusion: The proposed PFD will increase the locking capability on the both rise and fall edge w.r.t. the reference and the feedback signal. The input Frequency can be taken up to 5 gigahertz. The power supply is taken to be 1 V. The proposed PFD circuit will have a less number of transistors and also a low consumption of power 7.14 mW.

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