Large-Area Automated Layout Extraction Methodology for Full-IC Reverse Engineering

2018 ◽  
Vol 2 (4) ◽  
pp. 322-332
Author(s):  
Raul Quijada ◽  
Roger Dura ◽  
Jofre Pallares ◽  
Xavier Formatje ◽  
Salvador Hidalgo ◽  
...  
Author(s):  
Ronald Wilson ◽  
Domenic Forte ◽  
Navid Asadizanjani ◽  
Damon L. Woodard

Abstract In the hardware assurance community, Reverse Engineering (RE) is considered a key tool and asset in ensuring the security and reliability of Integrated Circuits (IC). However, with the introduction of advanced node technologies, the application of RE to ICs is turning into a daunting task. This is amplified by the challenges introduced by the imaging modalities such as the Scanning Electron Microscope (SEM) used in acquiring images of ICs. One such challenge is the lack of understanding of the influence of noise in the imaging modality along with its detrimental effect on the quality of images and the overall time frame required for imaging the IC. In this paper, we characterize some aspects of the noise in the image along with its primary source. Furthermore, we use this understanding to propose a novel texture-based segmentation algorithm for SEM images called LASRE. The proposed approach is unsupervised, model-free, robust to the presence of noise and can be applied to all layers of the IC with consistent results. Finally, the results from a comparison study is reported, and the issues associated with the approach are discussed in detail. The approach consistently achieved over 86% accuracy in segmenting various layers in the IC.


2015 ◽  
Vol 21 (S3) ◽  
pp. 921-922
Author(s):  
C. A. Brantner ◽  
M. Rasche ◽  
K. E. Burcham ◽  
J. Klingfus ◽  
J. E. Sanabia ◽  
...  

Author(s):  
Joseph Klingfus ◽  
Kevin Burcham ◽  
Martin Rasche ◽  
Thomas Borchert ◽  
Niklas Damnik

Abstract Chipscanning is the high-resolution, large-area, SEM image capture of complete (or partial) IC devices. Images are acquired sequentially in matrix-array fashion over an area of interest and large image mosaics are created from the collection of smaller images. Chipscanning is of keen interest to those involved with component obsolescence, design verification, anti-counterfeiting, etc. Chipscanning, and subsequent processing of the images, can also be used to reverse engineer an IC device. The reverse engineering process can be broken down into three main tasks; sample preparation, data collection, and data processing. We present practical insight into the data collection and data processing tasks and discuss an instrument platform uniquely suited for imaging such devices.


Author(s):  
Roger Durà ◽  
Jofre Pallarès ◽  
Raúl Quijada ◽  
Xavier Formatjé ◽  
Salvador Hidalgo ◽  
...  

Abstract This paper proposes a compact and robust topology descriptor for the automated identification of logic gates during the reverse engineering of full integrated circuits (ICs). This gate signature proves to be very insensitive to technology scaling, device sizing or layout extraction accuracy. Based on this new descriptor, an automated gate identification tool named Gate-X is implemented on top of commercial IC design tools. The speed tests for a practical 100k-gate digital IC example show that the complete sea of gates can be identified in a few hours.


2016 ◽  
Vol 24 (5) ◽  
pp. 28-33 ◽  
Author(s):  
Christine A. Brantner ◽  
Martin Rasche ◽  
Kevin E. Burcham ◽  
Joseph Klingfus ◽  
Joel Fridmann ◽  
...  

Author(s):  
J.R. Fridmann ◽  
J.E. Sanabia ◽  
M. Rasche

Abstract For large area, high resolution SEM imaging applications, such as integrated circuit (IC) reverse engineering and connectomics [1-3], SEM instruments are limited by small, uncalibrated fields of view (FOVs) and imprecise sample positioning. These limitations affect image capture throughput, requiring more stage drive time and larger image overlaps. Furthermore, these instrument limitations introduce stitching errors in 4 dimensions of the image data, X, Y, Z and I (signal intensity). Throughput and stitching errors are cited challenges [2] and software alone cannot tenably correct stitching errors in large image datasets [3]. Furthermore, software corrections can introduce additional errors into the image data via the scaling, rotation, and twisting of the images. So software has proven insufficient for reverse engineering of modern integrated circuits. Our methodology addresses the challenges brought on by small, uncalibrated FOVs and imprecise sample positioning by combining the resolution and flexibility of the SEM instrument with the accuracy (of the order 10 nm), stability, and automation of the electron beam lithography (EBL) instrument. With its unique combination of high resolution SEM imaging (up to 50,000 pixels x 50,000 pixels for each image), laser interferometer stage positioning, and FOV mapping, the reverse engineering scanning electron microscope (RE-SEM) produces the most accurate large area, high resolution images directly acquired by an SEM instrument [4]. Since the absolute position of each pixel is known ultimately to the accuracy afforded by the laser interferometer stage, these images can be stacked (3D-stitched) with the highest possible accuracy. Thus, the RE-SEM has been used to successfully reconstruct a current PC-CPU at the 22 nm node.


Author(s):  
G. Lehmpfuhl

Introduction In electron microscopic investigations of crystalline specimens the direct observation of the electron diffraction pattern gives additional information about the specimen. The quality of this information depends on the quality of the crystals or the crystal area contributing to the diffraction pattern. By selected area diffraction in a conventional electron microscope, specimen areas as small as 1 µ in diameter can be investigated. It is well known that crystal areas of that size which must be thin enough (in the order of 1000 Å) for electron microscopic investigations are normally somewhat distorted by bending, or they are not homogeneous. Furthermore, the crystal surface is not well defined over such a large area. These are facts which cause reduction of information in the diffraction pattern. The intensity of a diffraction spot, for example, depends on the crystal thickness. If the thickness is not uniform over the investigated area, one observes an averaged intensity, so that the intensity distribution in the diffraction pattern cannot be used for an analysis unless additional information is available.


Author(s):  
C. B. Carter ◽  
J. Rose ◽  
D. G. Ast

The hot-pressing technique which has been successfully used to manufacture twist boundaries in silicon has now been used to form tilt boundaries in this material. In the present study, weak-beam imaging, lattice-fringe imaging and electron diffraction techniques have been combined to identify different features of the interface structure. The weak-beam technique gives an overall picture of the geometry of the boundary and in particular allows steps in the plane of the boundary which are normal to the dislocation lines to be identified. It also allows pockets of amorphous SiO2 remaining in the interface to be recognized. The lattice-fringe imaging technique allows the boundary plane parallel to the dislocation to be identified. Finally the electron diffraction technique allows the periodic structure of the boundary to be evaluated over a large area - this is particularly valuable when the dislocations are closely spaced - and can also provide information on the structural width of the interface.


Author(s):  
C. C. Ahn ◽  
S. Karnes ◽  
M. Lvovsky ◽  
C. M. Garland ◽  
H. A. Atwater ◽  
...  

The bane of CCD imaging systems for transmission electron microscopy at intermediate and high voltages has been their relatively poor modulation transfer function (MTF), or line pair resolution. The problem originates primarily with the phosphor screen. On the one hand, screens should be thick so that as many incident electrons as possible are converted to photons, yielding a high detective quantum efficiency(DQE). The MTF diminishes as a function of scintillator thickness however, and to some extent as a function of fluorescence within the scintillator substrates. Fan has noted that the use of a thin layer of phosphor beneath a self supporting 2μ, thick Al substrate might provide the most appropriate compromise for high DQE and MTF in transmission electron microcscopes which operate at higher voltages. Monte Carlo simulations of high energy electron trajectories reveal that only little beam broadening occurs within this thickness of Al film. Consequently, the MTF is limited predominantly by broadening within the thin phosphor underlayer. There are difficulties however, in the practical implementation of this design, associated mostly with the mechanical stability of the Al support film.


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