scholarly journals Reversible Gate Logic Adder with Parity Preserving Design

2021 ◽  
Vol 1 (2) ◽  
Author(s):  
Kannadasan K
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Error Detection ◽  
High Speed ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Main Challenge ◽  
Wide Range

Reversible logic circuits have drawn attention from a variety of fields, including nanotechnology, optical computing, quantum computing, and low-power CMOS design. Low-power and high-speed adder cells (like the BCD adder) are used in binary operation-based electronics. The most fundamental digital circuit activity is binary addition. It serves as a foundation for all subsequent mathematical operations. The main challenge today is to reduce the power consumption of adder circuits while maintaining excellent performance over a wide range of circuit layouts. Error detection in digital systems is aided by parity preservation. This article proposes a concept for a fault-tolerant parity- preserving BCD adder. To reduce power consumption and circuit quantum cost, the proposed method makes use of reversible logic gates like IG, FRG, and F2G. Comparing the proposed circuit to the current counterpart, it has fewer constant inputs and garbage outputting devices and is faster.

A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate

2015 ◽  
Vol 11 (1) ◽  
pp. 36-49
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Power Loss ◽  
Optical Computing ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Processing Unit ◽  
Quantum Cost ◽  
Central Processing ◽  
Control Circuits

In the recent scenario of microelectronic industry, the reversible logic is considered as the burgeonic technology for digital circuit designing. It deals with the aim to generate digital circuits with zero power loss characteristics. Optical computing, Nanotechnology, Low power CMOS design and Digital Signal Processing (DSP) processors are leading areas of development with the concept of reversible logic. Researchers have already proposed various subsystems of the computer for the creation of low power loss devices with the help of numerous available reversible logic gates. Here in this paper, the authors have proposed a new reversible gate named as CDSM gate with 4×4 size. This CDSM gate is used to design optimized 4-bit binary comparator. The optimization is improved as compared to the existing designs based on some significant performance parameters such as total number of gates, garbage outputs generated, constant inputs and quantum cost. Comparators are widely used in various computing applications such as counters, convertor, Central Processing Unit (CPU) and control circuits etc. The comparator circuits using reversible logic can be visualized as a low power loss subsystem for the development of improved digital systems.

A new design of a low-power reversible Vedic multiplier

2020 ◽  
Vol 18 (03) ◽  
pp. 2050002
Author(s):  
Meysam Rashno ◽  
Majid Haghparast ◽  
Mohammad Mosleh
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Reversible Logic ◽  
Arithmetic Circuits ◽  
Quantum Cost ◽  
Computing Systems ◽  
Vedic Multiplier ◽  
Wide Range ◽  
Logic Unit

In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.

Novel design of multiplexer and demultiplexer using reversible logic gates

2018 ◽  
Vol 7 (3.29) ◽  
pp. 80
Author(s):  
Veerendra Nath Nune ◽  
Addanki Purna R
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Logic Gates ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Reversible Logic Gates ◽  
Novel Design

Reversibility is the prominent technology in the recent era. In reversible logic the number output lines are equal to the number of input lines. In reversible logic the inputs are to be retrieved from the outputs. Reversible logic gates are user defined gates. Reversible logic owns its applications in various fields which include low power VLSI. In this paper multiplexer is implemented using QCA, SAM and QCA & SAM gate. Also demultiplexer is implemented using two new reversible logic gates RAMESH and RAMESH-1 gates. These designs are simulated and synthesized using Xilinx ISE 12.1 and Mentor Graphics tool. The result shows that the proposed designs are more efficient in terms of gate count, quantum cost and power consumption.  

Design of Combinational Circuits Using Reversible Decoder in Tanner Tools

2020 ◽  
Vol 17 (4) ◽  
pp. 1743-1751
Author(s):  
R. Kannan ◽  
K. Vidhya
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Logic Gates ◽  
Full Adder ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Combinational Circuits ◽  
Nano Technology ◽  
Feynman Gate ◽  
Reversible Logic Gates

Reversible logic is the emerging field for research in present era. The aim of this paper is to realize different types of combinational circuits like full-adder, full-subtractor, multiplexer and comparator using reversible decoder circuit with minimum quantum cost. Reversible decoder is designed using Fredkin gates with minimum Quantum cost. There are many reversible logic gates like Fredkin Gate, Feynman Gate, Double Feynman Gate, Peres Gate, Seynman Gate and many more. Reversible logic is defined as the logic in which the number output lines are equal to the number of input lines i.e., the n-input and k-output Boolean function F(X1,X2,X3, ...,Xn) (referred to as (n,k) function) is said to be reversible if and only if (i) n is equal to k and (ii) each input pattern is mapped uniquely to output pattern. The gate must run forward and backward that is the inputs can also be retrieved from outputs. When the device obeys these two conditions then the second law of thermo-dynamics guarantees that it dissipates no heat. Fan-out and Feed-back are not allowed in Logical Reversibility. Reversible Logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc. Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption. The comparative study in terms of garbage outputs, Quantum Cost, numbers of gates are also presented. The Circuit has been implemented and simulated using Tannaer tools v15.0 software.

Estimation of Power for Reversible Subtractors

2018 ◽  
Vol 7 (4.5) ◽  
pp. 102
Author(s):  
E. V.Naga Lakshmi ◽  
Dr. N.Siva Sankara Reddy
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Garbage Output ◽  
Reversible Logic Gates

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG).   Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor.  Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.  

scholarly journals Low Power 32 x 32 – bit Reversible Vedic Multiplier

2019 ◽  
Vol 8 (10) ◽  
pp. 852-856
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Reversible Logic ◽  
Low Power Consumption ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
X 32

Recently, low-power consuming devices are gaining demand due to excessive use and requirement of hand-held & portable electronic gadgets. The quest for designing better options to lower the power consumption of a device is in high-swing. The paper proposes two 32 x 32 – bit multipliers. The first design is based only on the Urdhava Tiryakbhyam Sutra of Vedic Mathematics. The use of this sutra has created a multiplier with higher throughput and lesser power utilization than conventional 32 x 32 – bit multipliers. The second design incorporates the reversible logic into the first design, which further reduces the power consumption of the system. Thus bringing together Vedic sutra for multiplication and reversible gates has led to the development of a Reversible Vedic Multiplier which has both the advantages of high-speed and low-power consumption.

scholarly journals High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 725
Author(s):  
Xiaoran Li ◽  
Jian Gao ◽  
Zhiming Chen ◽  
Xinghua Wang
Keyword(s):  
Low Power ◽  
High Speed ◽  
Single Phase ◽  
Logic Gates ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Operating Frequency ◽  
Wide Range ◽  
Measurement Results ◽  
Phase Clock

This manuscript presents two novel low-power high-speed true-single-phase-clock (TSPC) prescalers with division ratios of 2/3 and 4/5, respectively, in a standard 90-nm CMOS technology. The logic gates incorporated between the D-flip-flops (DFFs) of a conventional 2/3 prescaler are modified to reduce the propagation delay and hence increase the maximum operating frequency. The measurement results show that the proposed divide-by-2/3 and divide-by-4/5 prescalers can operate up to 17 GHz and 15.3 GHz, respectively, which increase by 5.4 GHz and 4.3 GHz compared with conventional TSPC prescalers. The power of the proposed divide-by-2/3 prescaler is 0.67 mW and 0.92 mW, and 0.87 mW and 1.06 mW for the proposed divide-by-4/5 prescaler. The chip occupies an area of 20 × 35 μm2 and 20 × 50 μm2 for the proposed divide-by-2/3 and divide-by-4/5 prescalers.

scholarly journals A Novel Design and Evaluation of a Low Power Efficient Fault-Tolerant Reversible ALU Using QCA: Applications of Nanoelectronics

2021 ◽  
Author(s):  
Mary Swarna Latha Gade ◽  
Rooban S
Keyword(s):  
Low Power ◽  
High Speed ◽  
Fault Tolerant ◽  
Logic Gates ◽  
Reversible Logic ◽  
Functional Verification ◽  
Logical Operations ◽  
Arithmetic Logic Unit ◽  
Reversible Alu ◽  
Logic Unit

Abstract Reversible logic based on Quantum-dot Cellular Automata (QCA) is the most requirement for achieving nano-scale architecture that promises significantly high device integration density, high-speed calculation, and low power consumption. The arithmetic logic unit (ALU) is the significant component of a processor for processing and computing. The primary objective of this work is to develop a multi-layer fault-tolerant arithmetic logic unit using reversible logic in QCA technology. Additionally, the reversible ALU has divided into arithmetic (RAU) and a logic unit (RLU). A reversible 2:1 MUX using the Fredkin gate has been implemented to select either the arithmetic or logical operations. Besides, to improve the efficiency of arithmetic operations, a novel QCA reversible full adder is implemented. To build the ALU, fault-tolerant reversible logic gates are used. The proposed reversible multilayer QCA ALU is designed to carry out eight arithmetic and sixteen logical operations with a minimum number of gates, constant inputs, and garbage outputs compared to the existing works. The functional verification and simulation of the presented circuits are assessed by the QCADesigner tool.

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

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