Concepts of gain at an oxide-semiconductor interface and their application to the TETRAN—A tunnel emitter transistor—And to the MIS switching device

1986 ◽  
Vol 29 (3) ◽  
pp. 287-303 ◽  
Author(s):  
J.G. Simmons ◽  
G.W. Taylor
2017 ◽  
Vol 16 (1) ◽  
pp. 69-74
Author(s):  
Md Iktiham Bin Taher ◽  
Md. Tanvir Hasan

Gallium nitride (GaN) based metal-oxide semiconductor field-effect transistors (MOSFETs) are promising for switching device applications. The doping of n- and p-layers is varied to evaluate the figure of merits of proposed devices with a gate length of 10 nm. Devices are switched from OFF-state (gate voltage, VGS = 0 V) to ON-state (VGS = 1 V) for a fixed drain voltage, VDS = 0.75 V. The device with channel doping of 1×1016 cm-3 and source/drain (S/D) of 1×1020 cm-3 shows good device performance due to better control of gate over channel. The ON-current (ION), OFF-current (IOFF), subthreshold swing (SS), drain induce barrier lowering (DIBL), and delay time are found to be 6.85 mA/μm, 5.15×10-7 A/μm, 87.8 mV/decade, and 100.5 mV/V, 0.035 ps, respectively. These results indicate that GaN-based MOSFETs are very suitable for the logic switching application in nanoscale regime.


2019 ◽  
Vol 126 (18) ◽  
pp. 184501
Author(s):  
S.-H. Yoon ◽  
K. Kato ◽  
C. Yokoyama ◽  
D.-H. Ahn ◽  
M. Takenaka ◽  
...  

2015 ◽  
Vol 106 (12) ◽  
pp. 122902 ◽  
Author(s):  
Masafumi Yokoyama ◽  
Haruki Yokoyama ◽  
Mitsuru Takenaka ◽  
Shinichi Takagi

2013 ◽  
Vol 827 ◽  
pp. 282-286
Author(s):  
Gang Chen ◽  
Song Bai ◽  
Run Hua Huang ◽  
Yong Hong Tao ◽  
Ao Liu

SiC devices have excellent properties such as ultra low loss, high withstand voltage, large capacity, high frequency, and high temperature operation compared with Si devices. The SiC JFET is expected to be appropriate for the power device because a JFET has no oxide-semiconductor interface in the channel region and does not use the low mobility SiC MOSFET inversion layer as a channel. Forward I-V up to 4A for SiC VJFET, Gate voltage from 2V to 3.5V by step 0.5V. Reverse I-V characteristics up to 4500V (VG=-8V) for SiC VJFET, Gate voltage from-4V to-8V by step-2V. Turn-off characteristics are studied and fast turn-off time of 136ns at room temperature under DC voltage of 600V is successfully demonstrated.


Materials ◽  
2020 ◽  
Vol 13 (24) ◽  
pp. 5809
Author(s):  
Md. Mamunur Rahman ◽  
Ki-Yong Shin ◽  
Tae-Woo Kim

Frequency dispersion in the accumulation region seen in multifrequency capacitance–voltage characterization, which is believed to be caused mainly by border traps, is a concerning issue in present-day devices. Because these traps are a fundamental property of oxides, their formation is expected to be affected to some extent by the parameters of oxide growth caused by atomic layer deposition (ALD). In this study, the effects of variation in two ALD conditions, deposition temperature and purge time, on the formation of near-interfacial oxide traps in the Al2O3 dielectric are examined. In addition to the evaluation of these border traps, the most commonly examined electrical traps—i.e., interface traps—are also investigated along with the hysteresis, permittivity, reliability, and leakage current. The results reveal that a higher deposition temperature helps to minimize the formation of border traps and suppress leakage current but adversely affects the oxide/semiconductor interface and the permittivity of the deposited film. In contrast, a longer purge time provides a high-quality atomic-layer-deposited film which has fewer electrical traps and reasonable values of permittivity and breakdown voltage. These findings indicate that a moderate ALD temperature along with a sufficiently long purge time will provide an oxide film with fewer electrical traps, a reasonable permittivity, and a low leakage current.


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