A CRITICAL ANALYSIS OF A RELIABILITY STUDY OF BALL GRID ARRAY ELECTRONIC COMPONENTS SUBMITTED TO THERMAL AGING AND BOARD-LEVEL DROP TEST

2021 ◽  
pp. 105578
Author(s):  
Eduardo Franco de Monlevade ◽  
Idélcio Alexandre Palheta Cardoso ◽  
Gilberto Francisco Martha de Souza
Keyword(s):  
Thermal Aging ◽  
Critical Analysis ◽  
Ball Grid Array ◽  
Drop Test ◽  
Electronic Components ◽  
Reliability Study ◽  
Board Level

scholarly journals Reliability Study of Electronic Components on Board-Level Packages Encapsulated by Thermoset Injection Molding

2020 ◽  
Vol 4 (1) ◽  
pp. 26 ◽  
Author(s):  
Romit Kulkarni ◽  
Mahdi Soltani ◽  
Peter Wappler ◽  
Thomas Guenther ◽  
Karl-Peter Fritz ◽  
...  
Keyword(s):  
Injection Molding ◽  
Manufacturing Industry ◽  
Printed Circuit Boards ◽  
Thermal Loading ◽  
Operating Conditions ◽  
Raw Material ◽  
Electronic Components ◽  
Reliability Study ◽  
Encapsulation Process ◽  
Board Level

A drastically growing requirement of electronic packages with an increasing level of complexity poses newer challenges for the competitive manufacturing industry. Coupled with harsher operating conditions, these challenges affirm the need for encapsulated board-level (2nd level) packages. To reduce thermo-mechanical loads induced on the electronic components during operating cycles, a conformal type of encapsulation is gaining preference over conventional glob-tops or resin casting types. The availability of technology, the ease of automation, and the uncomplicated storage of raw material intensifies the implementation of thermoset injection molding for the encapsulation process of board-level packages. Reliability case studies of such encapsulated electronic components as a part of board-level packages become, thereupon, necessary. This paper presents the reliability study of exemplary electronic components, surface-mounted on printed circuit boards (PCBs), encapsulated by the means of thermoset injection molding, and subjected to cyclic thermal loading. The characteristic lifetime of the electronic components is statistically calculated after assessing the probability plots and presented consequently. A few points of conclusion are summarized, and the future scope is discussed at the end.

A Study on Repetitive Drop Test Method and for Electronic Component

2007 ◽  
Author(s):  
Qiang Yu ◽  
Masato Fujita ◽  
Tsuyoki Shibata ◽  
Takayoshi Katahira ◽  
Masaki Shiratori
Keyword(s):  
High Stress ◽  
Fem Simulation ◽  
Strain Analysis ◽  
Test Method ◽  
Drop Test ◽  
Electronic Components ◽  
Flat Bottom ◽  
Supporting Condition ◽  
Board Level ◽  
Load Conditions

In recent years, mobile phones have been miniaturized, so electronic components with high I/O count have been changed from QFP/SOIC to BGA/LGA. However BGA/LGA tends to have weak reliability for drop impact, and the drop reliability needs to be improved. For that, board level drop reliability has an important role in order to evaluate drop reliability for electronic components excluding influence from phone mechanics. This study focuses on the characterization of the test methods using experimental test, strain analysis and FEM simulation. In this paper, board level drop test shows drop a fixture with a component assembled on PWB. The drop test using a fixture with a flat bottom lacked of repeatability of failed drop count, and it was improved by adding hemisphere at the center on fixture bottom to reduce the influence by variation of falling posture angle, and strain analysis and the drop experimental proved it, too. The deformations of the fixture influence the test results, because the deformation of fixture caused high stress on solder joints. For that, the method to exclude the influence of fixture deformation was studied, and it was found that the influence can be decreased by supporting condition of PWB with a free-sliding end or the new design of the fixture. On the other hand, the effect of height of drop, mass of fixture, and supporting condition on the drop test, can be thought as the acceleration factors for the dropping load conditions. The drop tests were done in many load conditions. The results were analyzed by strain analysis and FEM simulation. As a result, an accelerating ratio can be evaluated by predicting the effect of these factors, and effective dropping test can be conduct without increasing the dropping height exceedingly.

Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Dynamic Responses ◽  
Circuit Board ◽  
Joint Stress ◽  
Printed Circuit ◽  
Increasing Demand ◽  
Improved Model ◽  
Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
Hung-Jen Chang ◽  
Chau-Jie Zhan ◽  
Tao-Chih Chang ◽  
Jung-Hua Chou
Keyword(s):  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit Board Assembly ◽  
Printed Circuit ◽  
Plastic Ball ◽  
Circuit Board Assembly ◽  
Halogen Free ◽  
Board Level ◽  
The Impact

In this study, a lead-free dummy plastic ball grid array component with daisy-chains and Sn4.0Ag0.5Cu Pb-free solder balls was assembled on an halogen-free high density interconnection printed circuit board (PCB) by using Sn1.0Ag0.5Cu solder paste on the Cu pad surfaces of either organic solderable preservative (OSP) or electroless nickel immersion gold (ENIG). The assembly was tested for the effect of the formation extent of Ag3Sn intermetallic compound. Afterward a board-level pulse-controlled drop test was conducted on the as-reflowed assemblies according to the JESD22-B110 and JESD22-B111 standards, the impact performance of various surface finished halogen-free printed circuit board assembly was evaluated. The test results showed that most of the fractures occurred around the pad on the test board first. Then cracks propagated across the outer build-up layer. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. Interfacial stresses numerically obtained by the transient stress responses supported the test observation as the simulated initial crack position was the same as that observed.

Failure Analysis of the Solder Joints in Flip-Chip BGA Packages under Free-Drop Test

2014 ◽  
Vol 936 ◽  
pp. 628-632 ◽  
Author(s):  
Guo Zheng Yuan ◽  
Xia Chen ◽  
Xue Feng Shu
Keyword(s):  
Flip Chip ◽  
Solder Joints ◽  
Ball Grid Array ◽  
Test Method ◽  
Drop Test ◽  
Test Reliability ◽  
Internal Crack ◽  
The Real ◽  
Plastic Ball ◽  
Free Drop

The failure of plastic ball grid array under intense dynamic loading was studied in the project. This paper presents the drop test reliability results of SnPb flip-chip on a standard JEDEC drop reliability test board. The failure mode and mechanism of planar array package in the drop test was comprehensively analyzed. High acceleration dropping test method was used to research the reliability of BGA (ball grid array) packages during the free-drop impact process. The model RS-DP-03A drop device was used to simulate the falling behavior of BGA chip packages under the real conditions, The drop condition meets the JEDEC22-B111 standards (pulse peak 1500g, pulse duration 0.5 ms) when dropping from the 650mm height . In the testing, according to the real-time changes of dynamic voltage, the relationship between drop times and different phases of package failure was analyzed. With the dye-penetrated method and optical microscopy, it was easy to observe the internal crack and failure locations. The growth mechanism of the cracks in solder joints under the condition of drop-free was analyzed and discussed.

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