Failure Analysis of the Solder Joints in Flip-Chip BGA Packages under Free-Drop Test

2014 ◽  
Vol 936 ◽  
pp. 628-632 ◽  
Author(s):  
Guo Zheng Yuan ◽  
Xia Chen ◽  
Xue Feng Shu

The failure of plastic ball grid array under intense dynamic loading was studied in the project. This paper presents the drop test reliability results of SnPb flip-chip on a standard JEDEC drop reliability test board. The failure mode and mechanism of planar array package in the drop test was comprehensively analyzed. High acceleration dropping test method was used to research the reliability of BGA (ball grid array) packages during the free-drop impact process. The model RS-DP-03A drop device was used to simulate the falling behavior of BGA chip packages under the real conditions, The drop condition meets the JEDEC22-B111 standards (pulse peak 1500g, pulse duration 0.5 ms) when dropping from the 650mm height . In the testing, according to the real-time changes of dynamic voltage, the relationship between drop times and different phases of package failure was analyzed. With the dye-penetrated method and optical microscopy, it was easy to observe the internal crack and failure locations. The growth mechanism of the cracks in solder joints under the condition of drop-free was analyzed and discussed.

2006 ◽  
Vol 128 (4) ◽  
pp. 441-448 ◽  
Author(s):  
S. Chaparala ◽  
J. M. Pitarresi ◽  
S. Parupalli ◽  
S. Mandepudi ◽  
M. Meilunas

One of the primary advantages of surface mount technology (SMT) over through-hole technology is that SMT allows the assembly of components on both sides of the printed circuit board (PCB). Currently, area array components such as ball grid array (BGA) and chip-scale package (CSP) assemblies are being used in double-sided configurations for network and memory device applications as they reduce the routing space and improve electrical performance (Shiah, A. C., and Zhou, X., 2002, “A Low Cost Reliability Assessment for Double-Sided Mirror-Imaged Flip Chip BGA Assemblies,” Proceedings of the Seventh Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 7–15, and Xie, D., and Yi, S., 2001, “Reliability Design and Experimental work for Mirror Image CSP Assembly”, Proceedings of the International Symposium on Microelectronics, Baltimore, October, pp. 417–422). These assemblies typically use a “mirror image” configuration wherein the components are placed on either side of the PCB directly over each other; however, other configurations are possible. Double-sided assemblies pose challenges for thermal dissipation, inspection, rework, and thermal cycling reliability. The scope of this paper is the study of the reliability of double-sided assemblies both experimentally and through numerical simulation. The assemblies studied include single-sided, mirror-imaged, 50% offset CSP assemblies, CSPs with capacitors on the backside, single-sided, mirror-imaged plastic ball grid arrays (PBGAs), quad flat pack (QFP)/BGA mixed assemblies. The effect of assembly stiffness on thermal cycling reliability was investigated. To assess the assembly flexural stiffness and its effect on the thermal cycling reliability, a three-point bending measurement was performed. Accelerated thermal cycling cycles to failure were documented for all assemblies and the data were used to calculate the characteristic life. In general, a 2X to 3X decrease in reliability was observed for mirror-image assemblies when compared to single-sided assemblies for both BGAs and CSPs on 62mil test boards. The reliability of mirror-image assemblies when one component was an area array device and the other was a QFP was comparable to the reliability of the single-sided area array assemblies alone, that is, the QFP had almost no influence on the double-sided reliability when used with an area array component. Moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux’s crack propagation method.


2002 ◽  
Vol 124 (3) ◽  
pp. 246-253 ◽  
Author(s):  
Y. W. Chan ◽  
T. H. Ju ◽  
Saeed A. Hareb ◽  
Y. C. Lee ◽  
Jih-Shun Wu ◽  
...  

A reliability model is established to study thermal fatigue behavior of solder joints in plastic ball grid array (PBGA) assemblies. The model is able to simulate a configuration with a large number of warpage affected solder joints. For efficient computation, regression models are used to calculate the force acting on each solder joint to determine its height under different warpage conditions. With the height and specified solder parameters, the shapes of selected solder joints are calculated using the Surface Evolver. In addition, the displacements of these solder joints can be determined by a macro model using equivalent beams to represent hundreds of solder joints. With the shapes and displacements, three-dimensional micro models for the selected joints are established to compute strain energy densities during temperature cycling. The energy densities can be used to estimate fatigue lives through an empirical correlation. Two PBGA assemblies with 72-I/O cavity-up and 540-I/O cavity-down packages are studied using the reliability model. Silicon chip size and substrate thickness are critical to solder fatigue in the cavity-up assembly. Their effects are reduced substantially for the cavity-down assembly, which is more reliable due to small global thermal mismatch. However, its reliability is strongly affected by the warpage. The warpage changes the shapes of solder joints and can reduce the corner joint’s fatigue life from 20,000 to 7800 temperature cycles for an arch-type warpage of 0.28 mm across a 42.5 mm×42.5 mm region.


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