scholarly journals Column-grid-array (CGA) versus ball-grid-array (BGA): board-level drop test and the expected dynamic stress in the solder material

2016 ◽  
Vol 27 (11) ◽  
pp. 11572-11582 ◽  
Author(s):  
E. Suhir ◽  
R. Ghaffarian
Keyword(s):  
Dynamic Stress ◽  
Ball Grid Array ◽  
Drop Test ◽  
Solder Material ◽  
Board Level

Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Dynamic Responses ◽  
Circuit Board ◽  
Joint Stress ◽  
Printed Circuit ◽  
Increasing Demand ◽  
Improved Model ◽  
Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

Elevated Stand-Off Heights in Solder Joint Interconnections of Surface Mounted IC Packages Result in Appreciable Stress and Warpage Relief

2018 ◽  
Vol 2018 (1) ◽  
pp. 000534-000542
Author(s):  
Ephraim Suhir ◽  
Sung Yi ◽  
Jennie S. Hwang ◽  
R. Ghaffarian
Keyword(s):  
Solder Joint ◽  
Solder Joints ◽  
Calculated Data ◽  
Ball Grid Array ◽  
Substantial Improvement ◽  
Stress Model ◽  
Solder Material ◽  
The Difference ◽  
Free Solder ◽  
Ic Package

Abstract The “head-in-pillow” (HnP) defects in lead-free solder joint interconnections of IC packages with conventional (small) stand-off heights of the solder joints, and particularly in packages with fine pitches, are attributed by many electronic material scientists to the three major causes: 1) attributes of the manufacturing process, 2) solder material properties and 3)design-related issues. The latter are thought to be caused primarily by elevated stresses in the solder material, as well as by the excessive warpage of the PCB-package assembly and particularly to the differences in the thermally induced curvatures of the PCB and the package. In this analysis the stress-and-warpage issue is addressed using an analytical predictive stress model. This model is a modification and an extension of the model developed back in 1980-s by the first author. It is assumed that it is the difference in the post-fabrication deflections of the PCB-package assembly that is the root cause of the solder materials failures and particularly and perhaps the HnP defects. The calculated data based on the developed analytical thermal stress model suggest that the replacement of the conventional ball-grid-array (BGA) designs with designs characterized by elevated stand-off heights of the solder joints could result in significant stress and warpage relief and, hopefully, in a lower propensity of the IC package to HnP defects as well. The general concepts are illustrated by a numerical example, in which the responses to the change in temperature of a conventional design referred to as ball-grid-array (BGA) and a design with solder joints with elevated stand-off heights referred to as column-grid-array (CGA) are compared. The computed data indicated that the effective stress in the solder material is relieved by about 40% and the difference between the maximum deflections of the PCB and the package is reduced by about 60%, when the BGA design is replaced by a CGA system. Although no proof that the use of solder joints with elevated stand-off heights will lessen the package propensity to the HnP defects is provided, the authors think that there is a reason to believe that the application of solder joints with elevated stand-off heights could result in a substantial improvement in the general IC package performance, including, perhaps, its propensity to HnP defects.

Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
Hung-Jen Chang ◽  
Chau-Jie Zhan ◽  
Tao-Chih Chang ◽  
Jung-Hua Chou
Keyword(s):  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit Board Assembly ◽  
Printed Circuit ◽  
Plastic Ball ◽  
Circuit Board Assembly ◽  
Halogen Free ◽  
Board Level ◽  
The Impact

In this study, a lead-free dummy plastic ball grid array component with daisy-chains and Sn4.0Ag0.5Cu Pb-free solder balls was assembled on an halogen-free high density interconnection printed circuit board (PCB) by using Sn1.0Ag0.5Cu solder paste on the Cu pad surfaces of either organic solderable preservative (OSP) or electroless nickel immersion gold (ENIG). The assembly was tested for the effect of the formation extent of Ag3Sn intermetallic compound. Afterward a board-level pulse-controlled drop test was conducted on the as-reflowed assemblies according to the JESD22-B110 and JESD22-B111 standards, the impact performance of various surface finished halogen-free printed circuit board assembly was evaluated. The test results showed that most of the fractures occurred around the pad on the test board first. Then cracks propagated across the outer build-up layer. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. Interfacial stresses numerically obtained by the transient stress responses supported the test observation as the simulated initial crack position was the same as that observed.

Failure Analysis of the Solder Joints in Flip-Chip BGA Packages under Free-Drop Test

2014 ◽  
Vol 936 ◽  
pp. 628-632 ◽  
Author(s):  
Guo Zheng Yuan ◽  
Xia Chen ◽  
Xue Feng Shu
Keyword(s):  
Flip Chip ◽  
Solder Joints ◽  
Ball Grid Array ◽  
Test Method ◽  
Drop Test ◽  
Test Reliability ◽  
Internal Crack ◽  
The Real ◽  
Plastic Ball ◽  
Free Drop

The failure of plastic ball grid array under intense dynamic loading was studied in the project. This paper presents the drop test reliability results of SnPb flip-chip on a standard JEDEC drop reliability test board. The failure mode and mechanism of planar array package in the drop test was comprehensively analyzed. High acceleration dropping test method was used to research the reliability of BGA (ball grid array) packages during the free-drop impact process. The model RS-DP-03A drop device was used to simulate the falling behavior of BGA chip packages under the real conditions, The drop condition meets the JEDEC22-B111 standards (pulse peak 1500g, pulse duration 0.5 ms) when dropping from the 650mm height . In the testing, according to the real-time changes of dynamic voltage, the relationship between drop times and different phases of package failure was analyzed. With the dye-penetrated method and optical microscopy, it was easy to observe the internal crack and failure locations. The growth mechanism of the cracks in solder joints under the condition of drop-free was analyzed and discussed.

Reliability of Underfilled Chip Scale Packages Attached With Heat Sink

2005 ◽  
Author(s):  
Saketh Mahalingam ◽  
Ashutosh Joshi ◽  
Joseph Lacey ◽  
Kunal Goray
Keyword(s):  
Solder Joint ◽  
Heat Sink ◽  
Operating Temperature ◽  
Ball Grid Array ◽  
Solder Joint Reliability ◽  
Proper Understanding ◽  
Joint Reliability ◽  
Board Level ◽  
Inelastic Strains ◽  
Underfill Material

Chip Scale Packages (CSP) are ideal intermediates between Direct Chip Attach (DCA) and Ball Grid Array (BGA) technologies in terms of both size and cost. Depending upon the application, chip scale packages are either underfilled for better solder joint reliability or are attached with a heat sink to keep the operating temperature of the chip under control. In many applications, as discussed in this paper, both an underfill and a heat sink are required. Quite expectedly the addition of two more materials, heat sink and adhesive, in the board level assembly results in fresh reliability concerns. In particular, the requirements on the underfill material and the heat sink attach adhesive are more rigorous and needless to say, a proper understanding of process and material issues is needed to make such a choice. The inelastic strains experienced by the solder joint (related to the underfill) and the peeling stresses at the heat sink attach adhesive interfaces (related to the thermal adhesive) are used as metric for comparing the number of material choices that are available. Based on the results, it is shown that it is important to choose materials that are thermo-mechanically matched with the rest of the system.

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