Monomolecular-layer assembly of oligothiophene on glass wafer surface and its fluorescence sensitization by formaldehyde vapor

2009 ◽  
Vol 202 (2-3) ◽  
pp. 178-184 ◽  
Author(s):  
Taihong Liu ◽  
Gang He ◽  
Meini Yang ◽  
Yu Fang
Author(s):  
Kevin Kröhnert ◽  
M. Wöhrmann ◽  
N. Jürgensen ◽  
K. D. Lang ◽  
T. Galler ◽  
...  

In this work we demonstrate the fabrication and use of a glass interposer platform with Through Glass Vias (TGVs) for high frequency applications. The platform is part of a versatile hermetically sealed glass package including passive and active devices (radar sensor, pressure sensors, infrared sensors). Glass has ideal properties for such applications, like excellent chemical resistance, mechanical strength and low costs. The hermetic sealing allows the seamless operation in hazardous environments. The TGVs may be deployed, for instance, in miniaturized sensor systems as vertical DC and RF interconnections with reduced parasitics for improved performance of the sealed device, while maintaining the hermetic sealing. TGVs provide a superior RF performance compared to bonding wires for frequencies >20 GHz and will provide larger bandwidths. TGVs improve the performance drastically and will give us an easy way to provide a hermitically sealed connection to the inner circuitries of the package. We investigate the whole process chain of the fabrication of the metallized TGVs. Initially 200 mm glass wafer with a thickness of 500 μm are used. Vias are created by laser-induced deep etching (LIDE). Subsequently, selective metallization of wafer surface areas and TGV sidewalls is carried out. Vias with diameters ranging from 50 μm to 1mm are created. The wafer thickness is reduced to 465 μm during the via production. Thus vias with an aspect ratio of 1:9 to 2:1 are created on one wafer. The vias with the high-aspect ratio are filled by sputtering with an appropriate seed layer for electroplating. Depending on the via geometry and the aspect ratio, normal DC sputtering is not viable. Thus, High Power Impulse Magnetron Sputtering (HIPIMS) is utilized to deposit a thin film of titanium and copper. Titanium served as the adhesion layer and copper is used as the conductive seed layer for the following electroplating step. Then, electroplating is carried out to line the different sized TGVs and create a conducting path through the wafer. Afterwards, the metallization in the vias has to be exposed by removing only the plated copper and sputtered titanium on top of the wafer by a combination of etching and chemical mechanical polishing. In the following steps, the front and backside are sputtered and coated with a resist to allow electroplating of the RDL on both backside and front side. Finally, the wafer is diced and measured. The LIDE process shows excellent repeatability with respect to the position and shape of the TGVs on all axes. The repeatability of the shape is critical for the following TGV metallization and the matching of the simulated RF behaviour compared to the behaviour of the fabricated structures. The metallization process of the TGVs shows very promising results regarding the repeatability of the formation of the TGVs and the metallization inside the vias. Different shapes and dimensions of vias could be metallized with the same process, which makes it stable against deviations in the structures to be fabricated on the wafer The measured RF properties of the realized structures are very promising and showing that the usage of glass and TGVs improves the performance in the millimetre wave regime significantly, compared to conventional bonding wires.


2006 ◽  
Vol 15 (4) ◽  
pp. 245-250
Author(s):  
Jong-Seok Kim ◽  
Kwang-Woo Nam ◽  
Sung-Hoon Choa ◽  
Jae-Hong Kwon ◽  
Byeong-Kwon Ju
Keyword(s):  

TAPPI Journal ◽  
2009 ◽  
Vol 8 (6) ◽  
pp. 29-35 ◽  
Author(s):  
PEDRAM FATEHI ◽  
LIYING QIAN ◽  
RATTANA KITITERAKUN ◽  
THIRASAK RIRKSOMBOON ◽  
HUINING XIAO

The application of an oppositely charged dual polymer system is a promising approach to enhance paper strength. In this work, modified chitosan (MCN), a cationic polymer, and carboxymethyl cellulose (CMC), an anionic polymer, were used sequentially to improve paper strength. The adsorption of MCN on cellulose fibers was analyzed via polyelectrolyte titration. The formation of MCN/CMC complex in water and the deposition of this complex on silicon wafers were investigated by means of atomic force microscope and quasi-elastic light scattering techniques. The results showed that paper strength was enhanced slightly with a layer-by-layer assembly of the polymers. However, if the washing stage, which was required for layer-by-layer assembly, was eliminated, the MCN/CMC complex was deposited on fibers more efficiently, and the paper strength was improved more significantly. The significant improvement was attributed to the extra development of fiber bonding, confirmed further by scanning electron microscope observation of the bonding area of fibers treated with or without washing. However, the brightness of papers was somewhat decreased by the deposition of the complex on fibers. Higher paper strength also was achieved using rapid drying rather than air drying.


2014 ◽  
Vol 13 (2) ◽  
pp. 127-140
Author(s):  
Snur Muhammad Amin Hassan ◽  
Azad Kareem Saeed ◽  
Nabil Abdul-Massih Salmo ◽  
Ahmed Hamdi Mehdi ◽  
Nali Abdulqadr Maaruf

1998 ◽  
Author(s):  
Tomasz Brozek ◽  
James Heddleson

Abstract Use of non-contact test techniques to characterize degradation of the Si-SiO2 system on the wafer surface exposed to a plasma environment have proven themselves to be sensitive and useful in investigation of plasma charging level and uniformity. The current paper describes application of the surface charge analyzer and surface photo-voltage tool to explore process-induced charging occurring during plasma enhanced chemical vapor deposition (PECVD) of TEOS oxide. The oxide charge, the interface state density, and dopant deactivation are studied on blanket oxidized wafers with respect to the effect of oxide deposition, power lift step, and subsequent annealing.


Author(s):  
Younan Hua ◽  
Bingsheng Khoo ◽  
Henry Leong ◽  
Yixin Chen ◽  
Eason Chan ◽  
...  

Abstract In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.


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