Renewed interest in flip-chip technologies in concurrently motivated in many application areas by such factors as the rising cost of gold used for wire bonding, the need for low thickness devices, continued CMOS downscaling, higher currents and temperatures, and lower voltages.
Today, many sophisticated devices can no longer be packaged with wire bonding technology and the mobile applications are more and more requiring footprint and weight reduction coupled with higher electrical performances (signal propagation and power distribution). The emergence of the 28nm CMOS technology node in particular, poses new quality and reliability constraints on interconnect technologies so as to cope with the increasing fragility of the back end of line, which may disqualify wire bonding for good. Not to mention the ever increasing IO density, making it necessary to develop new bumping and substrate technologies. It is not any longer only about higher performance and lower cost reliable interconnect, assembly and packaging technologies: if remained unresolved, the above constraints will prove to be bottlenecks if not obstacles to the continuation of Moore's law.
In this presentation, we will first focus on Flip-Chip technologies and their evolution. We will present the main players, their facilities and technologies. We will sketch a worldwide roadmap of flip-chip featuring such varied applications as wireless digital, PC processors, RF and power devices. We will then present our market forecasts and explain how we see these innovations will modify the market of packaging interconnections and assembly in the years to come.
Experimental Reliability Improvement of Power Devices Operated Under Fast Thermal Cycling