Thermo-mechanical finite element analysis in a multichip build up substrate based package design

2004 ◽  
Vol 44 (4) ◽  
pp. 611-619 ◽  
Author(s):  
Xiaowu Zhang ◽  
E.H. Wong ◽  
Charles Lee ◽  
Tai-Chong Chai ◽  
Yiyi Ma ◽  
...  
2013 ◽  
Vol 2013 (1) ◽  
pp. 000094-000099 ◽  
Author(s):  
Laura Mirkarimi ◽  
Rajesh Katkar ◽  
Ron Zhang ◽  
Rey Co ◽  
Zhijun Zhao

We are developing a new solution for wide I/O package on package applications, which is Bond Via Array (BVA) technology. The prototype vehicle built in this study has 1020 I/O's at a pitch of 0.24 mm with a high aspect ratio of approximately 10:1 and is ≤1.4 mm tall. PoP applications require large bandwidth and thinner packages challenging package developers to address warpage control for high yield processes. The design optimization of this package was established through rigorous finite element analysis of materials selection and structural modifications. The simulation methodology was validated by measuring the warpage as a function of temperature for the experimental prototypes. The details for the simulation and verification processes for the wide I/O process will be discussed. The variation between finite element analysis predictions and the experimental builds was ~10%, which allowed us to complete package design optimization with our simulation tools. The prototype build includes a standard and a low CTE substrate.


2001 ◽  
Author(s):  
Tiao Zhou

Abstract Reliability issues are discussed for a plastic laminate-based package with partially exposed die active area. Thermal-mechanical stresses are calculated with finite element analysis to examine the effect of encapsulant in comparison with a similar package with die fully encapsulated. Different material and geometry configurations are studied to assess the optimization of the package design.


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