A programmable checker for automated 2.5D/3D IC latch-up verification and hot junctions detection

Abstract Latch-up induced during High Temperature Operating Life (HTOL) test of a mixed signal device fabricated with 1.0 μm CMOS, double poly, double metal process caused failures due to an open in aluminum metal line. Metal lines revealed wedge voids of about 50% of the line width. Triggering of latch up mechanism during the HTOL test resulted in a several fold increase of current flowing through the ground metal line. This increase in current resulted in the growth of the wedge voids leading to failures due to open metal lines.

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A Silicon Debugging Methodology on Customer Prototype for Wafer Foundries

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0411 ◽

2012 ◽

Author(s):

Mai Zhihong ◽

Ng Tsu Hau ◽

Dawood M. Khalid ◽

Tan Pik Kee ◽

Jeffrey Lam

Keyword(s):

Case Studies ◽

Semiconductor Industry ◽

Full Information ◽

Limited Information ◽

Ip Protection ◽

First Case ◽

Silicon Debugging ◽

Failure Location ◽

Device Chip ◽

Latch Up

Abstract IP protection is of major importance for a semiconductor company and only limited information is made available for device debugging for the product outsourced to a foundry. In order to position ourselves better in the ever competitive semiconductor industry, with the consideration of IP protection, we have to provide the customers with the Si debugging capability and device/chip verification services in foundry. This paper explores the Si debugging methodology and technique in a foundry. Two case studies are presented and discussed. The first case illustrates the isolation of the failure location by InGaAs microscopy, upon which the failure was identified to be caused by a latch-up issue. In the second case, due to confidentiality considerations from the customer, full information could not be provided to the foundry for silicon debugging. The paper illustrates the ability to effectively debug a failure despite being constrained by limited information from the customer.

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РАДИАЦИОННО СТОЙКОЕ КМОП СТАТИЧЕСКОЕ ОЗУ 16 МБИТ 1657РУ2У

Nanoindustry Russia ◽

10.22184/1993-8578.2020.13.3s.169.174 ◽

2020 ◽

Vol 96 (3s) ◽

pp. 169-174

Author(s):

Ю.М. Герасимов ◽

Н.Г. Григорьев ◽

А.В. Кобыляцкий ◽

Я.Я. Петричкович

Keyword(s):

Total Dose ◽

Heavy Particles ◽

Topological Features ◽

Radiation Hardened ◽

Latch Up

Рассматриваются архитектурные, схемотехнические и конструктивно-топологические особенности асинхронного радиационно стойкого ОЗУ 1657РУ2У емкостью 16 Мбит с организацией (1Мx16)/(2Mx8), изготавливаемого по коммерческой КМОП-технологии объемного кремния уровня 130 нм. СБИС ОЗУ нечувствительна к эффекту «защелкивания», имеет повышенные дозовую стойкость и сбоеустойчивость при воздействии отдельных ядерных частиц (ОЯЧ), протонов и нейтронов (ТЧ). The paper highlights architectural, schematic and topological features of the radiation hardened 16 Mbit CMOS SRAM with configurable organization 1Mx16/2Mx8, which is immune to latch-up and with improved total dose and heavy particles tolerance.

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