Frequency stability optimization of an OEO using phase-locked-loop and self-injection-locking

2017 ◽  
Vol 386 ◽  
pp. 27-30 ◽  
Author(s):  
Rongrong Fu ◽  
Xiaofeng Jin ◽  
Yanhong Zhu ◽  
Xiangdong Jin ◽  
Xianbin Yu ◽  
...  
2003 ◽  
Vol 1 ◽  
pp. 197-200
Author(s):  
M. R. Kühn ◽  
E. M. Biebl

Abstract. An increasing number of applications is proposed for the 24 GHz ISM-band, like automotive radar systems and short-range communication links. These applications demand for oscillators providing moderate output power of a few mW and moderate frequency stability of about 0.5%. The maximum oscillation frequency of low-cost off-theshelf transistors is too low for stable operation of a fundamental 24GHz oscillator. Thus, we designed a 24 GHz first harmonic oscillator, where the power generated at the fundamental frequency (12 GHz) is reflected resulting in effective generation of output power at the first harmonic. We measured a radiated power from an integrated planar antenna of more than 1mW. Though this oscillator provides superior frequency stability compared to fundamental oscillators, for some applications additional stabilization is required. As a low-cost measure, injection locking can be used to phase lock oscillators that provide sufficient stability in free running mode. Due to our harmonic oscillator concept injection locking has to be achieved at the first harmonic, since only the antenna is accessible for signal injection. We designed, fabricated and characterized a harmonic oscillator using the antenna as a port for injection locking. The locking range was measured versus various parameters. In addition, phase-noise improvement was investigated. A theoretical approach for the mechanism of first harmonic injection locking is presented.


Author(s):  
Л.А. Цырульникова ◽  
А.Р. Сафин

We consider the neuromorphic dynamics of a filter-free phase locked loop with a phase modulation of a reference oscillator. The transition from pulsed single-spike dynamics to the bursting dynamics can be easily controlled by changing the depth and frequency of phase modulation, as well as the gain factor along the ring of the phase locked loop. The possibility of implementing neuromorphic calculations of the "OR" type in the scheme of three phase locked loops mutually coupled through a common control circuit is shown. The presented results can be used in the design of hardware-implemented neuromorphic networks with increased frequency stability, resistant to noise influences.


2017 ◽  
Vol 46 (4) ◽  
pp. 423002
Author(s):  
郑俊超 ZHENG Jun-chao ◽  
金韬 JIN Tao ◽  
池灏 CHI Hao ◽  
童国川 TONG Guo-chuan ◽  
朱翔 ZHU Xiang ◽  
...  

2013 ◽  
Vol 2013 ◽  
pp. 1-11 ◽  
Author(s):  
Sang-yeop Lee ◽  
Hiroyuki Ito ◽  
Shuhei Amakawa ◽  
Noboru Ishihara ◽  
Kazuya Masu

An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area: 0.11 mm2) by adopting 90 nm Si CMOS technology. The proposed circuit is configured with two cascaded PLLs; one of them is a reference PLL that generates reference signals to the other one from low-frequency external reference signals. The other is a main PLL that generates high-frequency output signals. A high-frequency half-integral subharmonic locking technique was used to decrease the phase noise characteristics. For a 50 MHz input reference signal, without injection locking, the 1 MHz offset phase noise was −88 dBc/Hz at a PLL output frequency of 7.2 GHz (= 144 × 50 MHz); with injection locking, the noise was −101 dBc/Hz (spur level: −31 dBc; power consumption from a 1.0 V power supply: 25 mW).


2018 ◽  
Vol 89 (1) ◽  
pp. 013103 ◽  
Author(s):  
C. F. Wu ◽  
X. S. Yan ◽  
J. Q. Huang ◽  
J. W. Zhang ◽  
L. J. Wang

2011 ◽  
Vol 403-408 ◽  
pp. 4252-4259
Author(s):  
Yu Liang Wang ◽  
Shuang Wei Han ◽  
Hong Sheng Li ◽  
Hao Liu

A program of digital phase locked loop (DPLL) drive is proposed to supply the gaps including debugging complex, easiness of interference and poor flexibility in the traditional analog drive loop of the silicon micro-machined gyroscope (SMG). The program, i.e. field programmable gate array (FPGA) is utilized to process the drive sensitive signal of the SMG after the analog to digital (A/D) processing of high-precision, has been utilized to achieve phase and amplitude closed-loop of the SMG’s drive mode. The simulation and test results show that the program has a great advantage to reduce the requirements on quality factor compared with the original program. When the gyroscope with a low quality factor is not easy to vibrate by the analog self-excited drive circuit, the program is adopted to reach drive mode’s frequency stability of 18ppm.


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