Voltage and oxide thickness dependent tunneling current density and tunnel resistivity model: Application to high-k material HfO2 based MOS devices

2017 ◽  
Vol 111 ◽  
pp. 628-641 ◽  
Author(s):  
N.P. Maity ◽  
Reshmi Maity ◽  
Srimanta Baishya
Keyword(s):  
Current Density ◽  
Tunneling Current ◽  
Oxide Thickness ◽  
Model Application ◽  
Mos Devices ◽  
High K ◽  
Resistivity Model

A tunneling current density model for ultra thin HfO2 high-k dielectric material based MOS devices

2016 ◽  
Vol 95 ◽  
pp. 24-32 ◽  
Author(s):  
Niladri Pratap Maity ◽  
Reshmi Maity ◽  
R.K. Thapa ◽  
Srimanta Baishya
Keyword(s):  
Current Density ◽  
Dielectric Material ◽  
Tunneling Current ◽  
Density Model ◽  
Mos Devices ◽  
High K ◽  
High K Dielectric

Modeling and Simulation of Tunneling Current Density for Ultra Thin MOS Devices

2016 ◽  
Vol 860 ◽  
pp. 30-34 ◽  
Author(s):  
Niladri Pratap Maity ◽  
Reshmi Maity ◽  
R.K. Thapa ◽  
S. Baishya
Keyword(s):  
Current Density ◽  
Current Flow ◽  
Tunneling Current ◽  
Oxide Thickness ◽  
Oxide Semiconductor ◽  
Tunneling Model ◽  
Mos Devices ◽  
Theoretical Predictions ◽  
Numerical Device ◽  
Mos Gate

In this paper, an analytical model for evaluation of tunneling current density of ultra-thin Metal Oxide Semiconductor (MOS) devices is presented. Results have been obtained for a wide variation of oxide thickness and biasing condition having doping concentration of 1 x 1017 cm-3. The investigation for the tunneling current density is limited to low temperatures, so that any thermal involvement to current flow can be neglected. The self-consistent oxide tunneling model has been used for device simulation, which is simple to implement and assist in the study of deep sub-micron MOS gate current effects, therefore correctly calculate the terminal current. Tunnel resistivity is also evaluated utilizing this tunneling current density model. Theoretical predictions are compared with the results obtained by the 2-D numerical device simulator ATLAS, good agreements between the two are observed.

scholarly journals Current Tunnelling in MOS Devices with Al2O3/SiO2 Gate Dielectric

2008 ◽  
Vol 2008 ◽  
pp. 1-5 ◽  
Author(s):  
A. Bouazra ◽  
S. Abdi-Ben Nasrallah ◽  
M. Said ◽  
A. Poncet
Keyword(s):  
Dielectric Constant ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Gate Leakage ◽  
Mos Devices ◽  
High K ◽  
Carrier Trap ◽  
High Dielectric ◽  
Very High ◽  
Tunnelling Current

With the continued scaling of the SiO2 thickness below 2 nm in CMOS devices, a large direct-tunnelling current flow between the gate electrode and silicon substrate is greatly impacting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. Despite its not very high dielectric constant (∼10), Al2O3 has emerged as one of the most promising high-k candidates in terms of its chemical and thermal stability as its high-barrier offset. In this paper, a theoretical study of the physical and electrical properties of Al2O3 gate dielectric is reported including I(V) and C(V) characteristics. By using a stack of Al2O3/SiO2 with an appropriate equivalent oxide thickness of gate dielectric MOS, the gate leakage exhibits an important decrease. The effect of carrier trap parameters (depth and width) at the Al2O3/SiO2 interface is also discussed.

Gate Tunneling Current Predicting Model for Scaled NMOSFET Devices

2013 ◽  
Vol 772 ◽  
pp. 422-426
Author(s):  
Zhi Chao Zhao ◽  
Tie Feng Wu ◽  
Hui Bin Ma ◽  
Quan Wang ◽  
Jing Li
Keyword(s):  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Integral Approach ◽  
Predicting Model ◽  
Mos Devices ◽  
Gate Oxide Thickness ◽  
Novel Theory ◽  
Gate Tunneling ◽  
Thin Gate Oxide

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel theory gate tunneling current predicting model using integral approach is presented in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using HSPICE simulator. The simulation results in BSIM4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.

scholarly journals A Quantitative Analysis of Tunneling Current in A MOS Cell for A Low-Voltage Microcontroller

1998 ◽  
Vol 20 (3) ◽  
pp. 165-167 ◽  
Author(s):  
M. A. Grado-Caffaro ◽  
M. Grado-Caffaro
Keyword(s):  
Quantitative Analysis ◽  
Current Density ◽  
Low Voltage ◽  
Tunneling Current ◽  
Approximate Expression ◽  
Oxide Thickness ◽  
Charge Carriers

The tunneling current density in a MOS cell for a low-voltage microcontroller based on EEPROM is calculated for high electric strengths. Furthermore, this current density is discussed in terms of the oxide thickness and an approximate expression for the velocity of charge carriers is derived.

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